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T870(E)(A5)TAPRIL EXAMINATIONNATIONAL CERTIFICATELOGIC SYSTEMS N3(8080273)5 April (X-Paper)9:00–12:00Calculators may be NOT used.This question paper consists of 7 pages.

(8080273)-2-T870(E)(A5)TDEPARTMENT OF HIGHER EDUCATION AND TRAININGREPUBLIC OF SOUTH AFRICANATIONAL CERTIFICATELOGIC SYSTEMS N3TIME: 3 HOURSMARKS: 100INSTRUCTIONS AND INFORMATION1.Answer ALL the questions.2.Read ALL the questions carefully.3.Number the answers according to the numbering system used in this questionpaper.4.ALL the sketches and diagrams must be large, clear and neat.5.Keep questions and subsections of questions together.6.Show ALL the steps and calculations.7.Write neatly and legibly.

(8080273)-3-T870(E)(A5)TQUESTION 1: NUMBER SYSTEMS AND ARITHMETIC ELEMENTS1.11.2If X 6416, Y 248 and Z 1510, calculate the following:1.1.1The value of X in the octal number system(2)1.1.2The product of Y and Z in the binary number system(4)1.1.3X divided by Y in the binary number system(3)1.1.4Use 2's complement to subtract 1448 from X.(4)Complete the following TRUTH TABLE by filling in the missing binary digits.Write only the answer next to the question number (1.2.1–1.2.5) in theANSWER BOOK.A00001111InputsB 2.310011.2.4111.2.5TABLE 11.3Briefly describe a half-adder.QUESTION 2:2.1(5)(2)[20]CODES, DATA AND DATA COMMUNICATION, ENCODERS ANDDECODERSGive an example of each of the following codes:2.1.1Self-complementing weighted code2.1.2Non-weighted code(2 1)(2)2.2What does ASCII stand for?(2)2.3Give ONE function of an encoder.(2)

(8080273)2.4-4-T870(E)(A5)TConvert the following numbers to the indicated code:2.4.11111010011012421BCD code to decimal2.4.210310 to XS3 (excess 3) code(2 3)2.5(6)The following word is received at the end of a transmission data 111By using even parities, determine whether any faults occurred duringtransmission and if so, rectify the fault(s).(8)[20]QUESTION 3: LOGIC GATES, INTEGRATED CIRCUITS AND LOGIC FAMILIES3.1One way to think of logic gate types is to consider what input states guaranteea certain output state.For example, an AND gate could be described as the function whereby anyLOW input guarantees a LOW output.Identify what type of gate is represented by each of the following statements:3.23.1.1Any LOW input guarantees a HIGH output.3.1.2Any difference in the input guarantees a LOW output.3.1.3Any HIGH input guarantees a HIGH output.(3 2)(6)Show, by means of a circuit diagram, how diodes can be used to construct anOR gate.(5)

(8080273)3.3-5-Study FIGURE 1 below and answer the questions.3.3.1Copy the TRUTH TABLE below in your ANSWER BOOK and useFIGURE 1 above to complete hat type of logic gate is represented by output Z in FIGURE 1?3.3.3Draw the IEC symbolQUESTION 3.3.2.forthelogicgateidentifiedWhat is the minimum number of inputs that an AND gate can have?Copyright reserved(4)(2)in(2)(1)[20]Please turn over

(8080273)-6-T870(E)(A5)TQUESTION 4: MEMORY ELEMENTS AND MEMORIES4.1Choose an answer from COLUMN B that matches a description inCOLUMN A. Write only the letter (A–G) next to the question number(4.1.1–4.1.5) in the ANSWER BOOK.4.1.14.1.24.1.34.24.3COLUMN ATime required to change the voltage levelfrom 90% to 10%Minimum time the data signal should beheld steady before the clock event, so thatthe data is reliably sampled by the clockA flip-flop triggered by either the positiveedge or negative edge of the clock pulse4.1.4Time required to change the voltage levelfrom 10% to 90%4.1.5Minimum time for which the voltage levelsat the excitation inputs must remainconstant after the triggering edge of theclock pulse in order for the levels to bereliably clocked into the flip-flopACOLUMN Bedge triggeringBrising timeCholding timeDfalling timeElevel triggeringFdelay timeGsetup time(5 1)(5)Briefly explain the difference between a combinational- and a sequentialcircuit.(4)Study FIGURE 2 below and then answer the questions.FIGURE 24.3.14.3.2Copyright reservedWhen a 1 is applied to both the set (S) and reset (R) inputs of theflip-flop in FIGURE 2 above the outputs are termed to be invalid.Why are the outputs invalid?(2)Draw the IEC symbol for the flip-flop in FIGURE 2.(2)Please turn over

(8080273)4.44.5-7-T870(E)(A5)TDraw a labelled single-cell structure for a dynamic read-write memory(DRAM).(5)An SRAM cell has three different operating states of which one is standby.Name the remaining TWO modes of operation.(2)[20]QUESTION 5: SHIFT REGISTERS AND COUNTERS5.15.2Explain the working principle of a 4-bit SISO (series-in-series-out) shiftregister.Draw a neat, labelled sketch of 4-bit ring counter making use of a JK flip-flopwhich is negatively edged.TOTAL:Copyright reserved(12)(8)[20]100

MARKING GUIDELINENATIONAL CERTIFICATEAPRIL EXAMINATIONLOGIC SYSTEMS N35 APRIL This marking guideline consists of 8 pages.

MARKING GUIDELINE-2LOGIC SYSTEMS N3T870(E)(A5)TQUESTION 11.11.1.11.1.2X 6416 011001002 001 100 100 1448 Y 1448Y 248 and Z 151015 2248 84211111 1510 11112 4010 100 248 101002 11.1.3(2)10100x111110100101001010010100001011 0 0(4)X 6416 11001002Y 248 101001Copyright reserved010011010000011100000011011000 00010 00 (3)Please turn over

MARKING GUIDELINE1.1.4-3LOGIC SYSTEMS N3T870(E)(A5)TX 1100100211448 44001 100 100 1448 11001002 2's complement of 1100100 is equal to 0011011 1 0011100 1011 0 1.21.2.11.2.21.2.31.2.41.2.5carry*** 100100010010110000000 ignore(4)01101(5 1)1.3A half-adder is an arithmetic element which has two inputs and two outputs(sum and carry out), and it can add two bits at a time. (5)(2)[20]QUESTION 22.12.1.12421; 4221; 8421; 5211; 3321 or 43212.1.2Gray or XS3 code(Any 1)(1)(1)2.2American Standard Code for Information Interchange(2)2.3An encoder is used to convert decimal code to binary or BCD code.(2)2.42.4.1Copyright reserved1111 2421 9 0100 2421 4 1101 2421 5 Please turn over

MARKING GUIDELINE-4LOGIC SYSTEMS N32.4.21 1 34 0100 0 0 33 0011 T870(E)(A5)T3 3 36 0110 (6)(2 3)2.5111100101011100010001e1e1e1e 110111u001111001100eeee111u1e1e1ee The fault is in column 5, row 5, the 1 (one) is changed to a 0 (zero)111100101011100010001111Copyright reserved11010 1001111001100111111(8)[20]Please turn over

MARKING GUIDELINE-5LOGIC SYSTEMS N3T870(E)(A5)TQUESTION 33.13.1.1NAND gate3.1.2XNOR gate3.1.3OR gate(3 2)3.2(6)A Y- outputB 1 mark for direction ofdiode1 mark for rightconnection of diodes1 mark for resistor1 mark for output1 mark for earthing 3.33.3.1INPUTSA10103.3.2(5)XOR gateB1100OUTPUTSX 0100Y 0010Z 0110(4)(1 x 2)(2)3.3.3(2)3.4One (1)Copyright reserved(1)[20]Please turn over

MARKING GUIDELINE-6LOGIC SYSTEMS N3T870(E)(A5)TQUESTION 44.14.24.34.1.14.1.24.1.34.1.44.1.5DGABC(5 1)(5)A combinational circuit can be defined as a circuit of which the output isdependent only on the inputs at the same instant of time whereas asequential circuit can be defined as a circuit of which the output depends notonly on the present inputs but also on the past history of inputs.(4)4.3.1The outputs are invalid because the outputs of both Q and Q' go to0. This condition violates the fact that the outputs arecomplements of each other. SD4.3.2S(2) Q ClQRRD(2)4.4(5)4.5 Reading mode Writing modeCopyright reserved(2)[20]Please turn over

MARKING GUIDELINE-7LOGIC SYSTEMS N3T870(E)(A5)TQUESTION 55.11.2.3.4.5.6.7.8.9.10.Bit 0 is entered into the data input line. D1 0, first clock pulse isapplied, FF1 is reset and stores 0. Next bit 1 is entered. Q1 0, since Q1 is connected to D2, D2becomes 0. Second clock pulse is applied, the 1 on the input line is shifted intoFF1 because FF1 sets. The 0 which was stored in FF1 is shiftedinto FF2. Next bit 0 is entered and third clock pulse applied. 0 is entered intoFF1, 1 stored in FF1 is shifted to FF2 and 0 stored in FF2 is shiftedto FF3. Last bit 1 is entered and 4th clock pulse applied. 1 is entered intoFF1, 0 stored in FF1 is shifted to FF2, 1 stored in FF2 is shiftedto FF3 and 0 stored in FF3 is shifted to FF4. This completes theserial entry of 4-bit data into the register. Now the LSB 0 is on theoutput Q4. Clock pulse 5 is applied. LSB 0 is shifted out. The next bit 1appears on Q4 output. Clock pulse 6 is applied. The 1 on Q4 is shifted out and 0 appearson Q4 output. Clock pulse 7 is applied. 0 on Q4 is shifted out. Now 1 appears onQ4 output. Clock pulse 8 is applied. 1 on Q4 is shifted out. When the bits are being shifted out (on CLK pulse 5 to 8) moredata bits can be entered. (12)5.2OR

MARKING GUIDELINELOGIC SYSTEMS ight reserved100

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