VHDL 3 Finite State Machines FSM

VHDL 3 Finite State Machines FSM

VHDL 5. FSM ver.8a VHDL 5 FINITE STATE MACHINES (FSM) Some pictures are obtained from FPGA Express VHDL Reference Manual, it is accessible from the machines in the lab at /programs/Xilinx foundation series/VDHL reference manual /programs/Xilinx foundation series/foundation project manager/foundation help content/XVDHL compiler help pages 1 VHDL 5. FSM ver.8a Contents: You will learn Finite state machines FSMs Feedback using signals or variables Use of clocks, processes to make FSMs Different types of Finite State Machines Moore Mealy

2 VHDL 5. FSM ver.8a 3 Finite State machines FSM A system jumps from one state to the next within a pool of finite states upon clock edges and input transitions. (traffi c light, digital watch, CPU). VHDL 5. FSM ver.8a 4 TO WRITE CLOCK EDG ES Using if-then-else VHDL 5. FSM ver.8a 5

Clock edges: Use of if Statements or Wait until to represent Flip-flops Test for edge of a signal. if SIGNALevent and SIGNAL = 1 -- rising edge if SIGNALevent and SIGNAL = 0 -- falling edge Or In a wait statement, edge can also be wait until CLK = 1; -- rising edge triggered wait until CLK = 0;--falling edge triggered VHDL 5. FSM ver.8a 6 Use of Wait and If for clock edge detection Clock edge detection Synchronous processes clock edge detection: Use Wait or IF

Asynchronous processes clock edge detection: Use IF only VHDL 5. FSM ver.8a 7 Clock edges: compare wait and if Statements IEEE VHDL requires that a process with a wait state ment must not have a sensitivity list. In general, the following guidelines apply: Synchronous processes (processes that compute values on ly on clock edges) must be sensitive to the clock signal. Us e wait-until or if. When Wait is used: The first statement must be wait until, E.g. Process no sensitivity list, implies there is one clock as input

Begin Wait until clock =1 Asynchronous processes (processes that compute values o n clock edges and when asynchronous conditions are TRU E) must be sensitive to the clock signal (if any), and to inp uts that affect asynchronous behavior. Use if only. E.g. Process (clock, input_a, input_b) VHDL 5. FSM ver.8a 8 THE FEEDBACK CONC EPT For making FSM VHDL 5. FSM ver.8a 9 The feedback concept

So far you learned logic with feed forward paths only. Now, you will see feedback paths. The first step of the making a state machine VHDL 5. FSM ver.8a 10 Feedback 1 -- direct feedback 1) library IEEE;--(ok Vivado 2014.4 & ISE) 2) use IEEE.STD_LOGIC_1164.ALL; 3) entity some_entity is 4) port (a, clk, reset: in std_logic; 5) c : buffer std_logic); -- or use inout 6) end some_entity; b Q 7) ------------------------------------------D 8) architecture example of some_entity is a 9) begin 10) process(clk,reset) Clock

clk 11) begin reset 12) if reset = '1' then c <= '0'; 13) elsif rising_edge(clk) reset 14) then c<= not(a and c); If C is an IO pin connected outside, 15) end if; 16) end process; must have type inout or buffer 17) end example; -- synthesized ok c it VHDL 5. FSM ver.8a 11 Concentrate on the following lines of Feedback 1 Use of signals in a clocked process

13)elsif rising_edge(clk) 14) then c<= not(a and c); ****************Note *********** Current not(a and c) affects next b VHDL 5. FSM ver.8a 12 Worksheet 5.1 Initially c=0 Draw c Clock Reset a c b a D

Q Clock reset clk reset c 13 VHDL 5. FSM ver.8a Feedback 2 -- using signals 1) library IEEE;--(ok Vivado 2014.4 & ISE) 2) use IEEE.STD_LOGIC_1164.ALL; a D q b2 b1 Dq D

q c 3) entity some_entity is 4) port (a, clk, reset: in std_logic; clk Clock reset c : inout std_logic); -- or use inout 6) end some_entity; 7) ------------------------------------------reset 8) architecture example of some_entity is 9) signal b: std_logic; -- internal signal b is global, 10) begin 11) process(clk,reset) 12) begin 13) if reset = '1' then c <= '0'; If C is an IO pin connected outside, 14) elsif rising_edge(clk)

must have type inout or buffer 15) then b<= not(a and c); 16) c <= b; 17) end if; 18) end process; 19) end example; -- synthesized ok 5) it VHDL 5. FSM ver.8a 14 Concentrate on the following lines of feedback 2 Use of signals in a clocked process 15) then b<= not(a and c); 16) c <= b; ****************Note ***********

Current {not (a and c)} affects next b Previous (before 8 is executed) b affects c The two bs in the process have different states VHDL 5. FSM ver.8a Exercise 5.2 a Initially c=0,b1=1,b2=1 Draw b2,c Clock reset a b1 b2 c D q b2 b1 Dq D

clk reset 15 q Clock reset c VHDL 5. FSM ver.8a 16 Feedback 3 -- using variables 1) library IEEE;--(ok Vivado 2014.4 & ISE) 2) use IEEE.STD_LOGIC_1164.ALL; 3) entity some_entity is 4) port (a, clk, reset: in std_logic; c : buffer std_logic); -- or use inout 6) end some_entity;

7) ------------------------------------------v Q 8) architecture example of some_entity is a D 9) begin 10) Process -- no sensitivity list for 'wait unit' 11) variable v: std_logic; --v is local Clock clk 12) begin reset 13) wait until clk = '1'; reset 14) if reset = '1' then v := '0'; 15) else v := not (a and c); If C is an IO pin connected outside, 16) c <= v; must have type inout or buffer 17) end if; 18) end process;

5) c it VHDL 5. FSM ver.8a 17 Concentrate on the following lines of feedback 3 Use of signals in a clocked process 15) 16) else v := not (a and c); c <= v; ****************Note *********** Current not(a and c) affects next variable v The new variable (after line6 is executed) v affects c This is the main difference between signal and variable in a cl ocked process Signals do not change immediately

Variables change immediately 18 VHDL 5. FSM ver.8a Exercise 5.3 a Initially c=0 clk Draw c Clock Reset a c reset v

D Q Clock reset c 19 VHDL 5. FSM ver.8a Use of modes : inout and buffer in feedback Buffer can be read back inout allows for internal feedback, it can also read external signals. in out buffer

in in Inout out VHDL 5. FSM ver.8a 20 Important: Feedback using signals and variables will give different results. Variable: A variable in a process can update man y times. Signal: <= can be treated as a flip-flop (left side of <= is output, right side of <= is input) , it only updates once when the process executes at th e triggering clock edge. When a signal is assigned to different values by differ

ent statements in a process, only the last statement is effective. VHDL 5. FSM ver.8a Inside a process 21 The Trick!! Signals in a process: Combination process=the process has no clock edge detection: onl y the last assignment statement for that particular signal counts, th e assignment is a combinational logic circuit. Clocked process=the process has clock edge detection (e.g. if risi ng_edge(clk) ) Signal assignment before clock edge detection: same as combination p rocesses (same as above). Assignment after clock edge detection: the assignment is a flip-flop. Variables in processes (only live in processes anyway): w hen all signals are stable, then use your old programming

common sense. Assignments take effect immediately. VHDL 5. FSM ver.8a EXAMPLE TO SHOW The difference between signal and variables in feedback processes 22 VHDL 5. FSM ver.8a process( S1, S2 ) variable V1, V2: BIT; 23 (page 6-9 xilinx foundation4.2 vhdl reference) signal S1, S2: BIT; -signal S_OUT: BIT_VECTOR(1 to 8); begin V1 := 1; -- This sets the value of V1 V2 := 1; -- This sets the value of V2 S1 <= 1; -- This assignment is the driver for S1 S2 <= 1; -- This has no effect because of the

-- assignment later in this process S_OUT(1) <= V1; -- Assigns 1, the value assigned above S_OUT(2) <= V2; -- Assigns 1, the value assigned above S_OUT(3) <= S1; -- Assigns 1, the value assigned above S_OUT(4) <= S2; -- Assigns 0, the value assigned below V1 := 0; -- This sets the new value of V1 V2 := 0; -- This sets the new value of V2 S2 <= 0; -- This assignment overrides the -- previous one since it is the last assignment to this signal here S_OUT(5) <= V1; -- Assigns 0, the value assigned above S_OUT(6) <= V2; -- Assigns 0, the value assigned above S_OUT(7) <= S1; -- Assigns 1, the value assigned above S_OUT(8) <= S2; -- Assigns 0, the value assigned above end process; VHDL 5. FSM ver.8a (See 24 VHDL reference manual version : chapter 6 [sequential statements]: variable/signal assignm ent statements.)

signal S1, S2: BIT; signal S_OUT: BIT_VECTOR(1 to 8); ... process( S1, S2 ) variable V1, V2: BIT; begin V1 := 1; -- This sets the value of V1 V2 := 1; -- This sets the value of V2 S1 <= 1; -- This assignment is driver for S1 S2 <= 1; -- This has no effect because of the -- assignment later in this process VHDL 5. FSM ver.8a 25 S_OUT(1) <= V1; -- is 1, the value assigned above S_OUT(2) <= V2; -- is 1, the value assigned above S_OUT(3) <= S1; -- is 1, the value assigned above S_OUT(4) <= S2; -- is 0, the value assigned below V1 := 0; -- This sets the new value of V1 V2 := 0; -- This sets the new value of V2 S2 <= 0; -- This assignment overrides the

-- previous one since it is the last -- assignment to this signal in this -- process VHDL 5. FSM ver.8a 26 S_OUT(5) <= V1; -- is 0, the value assigned above S_OUT(6) <= V2; -- is 0, the value assigned above S_OUT(7) <= S1; -- is 1, the value assigned above S_OUT(8) <= S2; -- is 0, the value assigned above end process; VHDL 5. FSM ver.8a 27 Examples: signals and variables in process( ) See Roth p.66

Process --a variable can change value many times in a process variable v1: integer :=1; --initialized to1 variable v2: integer :=2; --initialized to 2 variable v3: integer :=3;--iniltialized to 3 begin wait on trigger; --find results after clock edge--------------- t1 t2 t3 t4 v1:=v2+v3; -- after t1, now v1 = 2+3=5 5 10 20 40 v2:=v1; -- after t1, now v2=5 5 10 20 40 v3:=v2;

-- after t1, now v3=5 5 10 20 40 sum<=v1+v2+v3; 15 30 60 120 -- so sum=5+5+5=15 after the first trigger clock edge. end process Variables case 28 VHDL 5. FSM ver.8a Exercise 5.4:Architecture sig_arc of example is signal s1: integer:=1; signal s2: integer:=2; Signal case signal s3: integer:=3; begin -- t1 is just after the first clk edge, etc process begin wait on clk;-t1 t2 t3 t4 s1<=s2+s3; -- s1=

s2<=s1; -- s2= s3<=s2; -- s3= sum<=s1+s2+s3;--sum= end process end __ __ __ __ __ __ __ __

__ __ __ __ __ __ __ __ VHDL 5. FSM ver.8a library IEEE; -- successfully compiled and tested;--(syn. ok Vivado 2014.4 ) use IEEE.STD_LOGIC_1164.all; -- so use reset to set them to init values use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity some_entity is

port ( clk : in STD_LOGIC; reset : in STD_LOGIC; sportsum: out integer); end some_entity; Architecture sig_arc of some_entity is

signal t1, t2, t3 : integer; -- In Xilinx, ini. Signals cannot be done begin -- t1 is just after the first clk, etc --with clk, without clk, with s1234, in sen. list or not process(clk,reset) -- clocked process, syn. input can be in or not in the sensitivity list -- begin wait on clk;-- t1 t2 t3 t4 begin if reset = '1 then -- use reset to set them to init values t1 <= 1; t2 <= 2; t3 <= 3; sportsum <= 0; elsif clk='1' and clk'event then t1<=t2+t3; -- s1= t2<=t1; --s2= t3<=t2; --s3= sportsum <= t1+t2+t3; -- sum= 6, 8, 9, 14 after each clock edge end if; end process; end sig_arc; 29 VHDL 5. FSM ver.8a

30 Exercise 5.5: architecture example of some_entity is signal con1: std_logic; -- b is global, bit is a VHDL type begin Plot result. process(clk,reset) Try this in lab and explain the result variable v1: std_logic;

begin if reset = '1' then out1 <= '0'; out2<='0'; out3<='0';con1<='1'; elsif rising_edge(clk) then ---case 1 ----- direct feedback out1<= not(in1 and out1); -- out1 is immediate ---case 2 ----- feedback using signal con1<= not(in1 and out2); out2<= con1; -- out2 is delayed hence lower frequency ---case 3 ----- feedback using variable v1:=not(in1 and out3); -- out3 is immediate out3 <= v1; end if; end process; end example; -- synthesized VHDL 5. FSM ver.8a Worksheet 5.5 Clock Reset Out1 Out2 Out3 Con1

31 Types of FSM Finite State machines -Study FSMs with inputs other than the clock FSM Moore machine Mealy machine VHDL 5. FSM ver.8a 32 VHDL 5. FSM ver.8a 33 State machine designs, 2 types A Moore machines outputs are a function of the present s tate only. A Mealy machines outputs are a function of the present-st

ate and present-inputs. 34 VHDL 5. FSM ver.8a Moore machine, an example F1 is B<= not (A and C) F2 is D<= not C Output is a function of the state registers. The simplest Moore machine use only one process , see next page Nand D type Flip-Flop (FF) not VHDL 5. FSM ver.8a 35

Moore machine example 1 architecture moore2_arch of system is 2 signal C: bit; -- global, can be seen by different 3 begin 4-- since D is purely for output, no feedback read 5 -- requirement, so it has the type out 6 D <= not C; -- F2 = combination logic 7-8 process -- sequential logic process 9 begin 10 wait until clock;

11 C <= not (A and C); --F1 = combination logic 12 end process; 13 end moore2_arch; VHDL 5. FSM ver.8a 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 17) 18) 19)

20) 21) 22) 23) 24) 36 library IEEE; -- Moore2 example ,-- synthesized ok. (ISE % Vivado 2014.4) use IEEE.std_logic_1164.all; entity some_entity is ---------------------------------------------port ( clock: in std_logic; A,reset: in std_logic; D: inout std_logic -- no need to use inout or buffer type, since there is no need to read. ); end some_entity; architecture moore2_arch of some_entity is signal B,C: std_logic; ---------------------------------------------begin process (C) -- combinational logic begin D <= not C; -- F2 = combination logic end process; process(clock,reset) -- sequential logic

begin if reset = '1' then c <= '0'; elsif rising_edge(clock)then C <= not (A and C); --F1 = combination logic end if; end process; end moore2_arch; VHDL 5. FSM ver.8a 37 Moore machine using 2 processes It is more flexible and easier to design. You can make it formal that F1 is an operation (a concurre nt line of code) and F2 is another operation (a process) 38 VHDL 5. FSM ver.8a Exercise 5.6 ,exercise on Moore machine, draw c (init. c=0) clock

C=/D when A=1 C=/D when A=1 C=/D when A=0 C=/D when A=0 Nand D type D type FF FF not VHDL 5. FSM ver.8a 39 Mealy machine A Mealy machines outputs are a function of the present st

ate and the inputs. 40 VHDL 5. FSM ver.8a Mealy machine, an example A Mealy Machine can use two processes, since its timing i s a function of both the clock and data inputs. F1 is C <= not(A or C); F2 is D <= (A or C) In the diagram we can say that B is the current output of not( A and C), but B does not need to exist, writing C <= n ot(A or C) is enough F1 is B <= not(A or C); F2 is D <= (A or C) D Nor Q D-Flip-Flop or

VHDL 5. FSM ver.8a 41 Mealy machine outputs are a function of the present state and the inputs. 1) 2) 3) 4) 5) 6) 7) 8) 9) 10) 11) 12) 13) 14) 15) 16) 17) 18)

19) 20) 21) 22) 23) 24) 25) library IEEE; -- Mealy example ,-- synthesized ok. ( Vivado 2014.4) use IEEE.std_logic_1164.all; entity some_entity is ---------------------------------------------port ( clock: in std_logic; A,reset: in std_logic; D: inout std_logic -- no need to use inout or buffer type, since there is no need to read. ); end some_entity; architecture mealy_arch of some_entity is signal C: std_logic; ---------------------------------------------begin process (A,C) -- combinational logic process begin D <= (A or C);--F2 = combination logic end process; --------------------------------------------process(clock,reset) -- sequential logic begin

if reset = '1' then c <= '0'; elsif rising_edge(clock)then C <=not(A or C);--F1 = combination logic end if; end process; end mealy_arch; Operation :F Operation 42 VHDL 5. FSM ver.8a Exercise 5.7: on Mealy machine, Plot C,D (init. c=0) clock clock A CA D C D F1 is B <= not(A or C); F2 is D <= (A or C)

D Nor Q D-Flip-Flop or VHDL 5. FSM ver.8a 43 Quick revision You should know How to write a clock edge detector Feedback theory and implementation Design Moore and Mealy machine Use of signal and variables and understand their differences

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    Title: Slide 1 Author: User Last modified by: Gareth Pitchford Created Date: 9/12/2006 12:54:36 AM Document presentation format: On-screen Show (4:3)