# Slide Title - users.encs.concordia.ca

CMOS Circuits CONCORDIA VLSI DESIGN LAB 1 Combination and Sequential CONCORDIA VLSI DESIGN LAB 2 Static Combinational Network CMOS Circuits VDD Pull-up network-PMOS Pull-down network- NMOS Networks are

complementary to each other When the circuit is dormant, no current flows between supply lines. Number of the NMOS transistors (PMOS transistors) equals to the number of the inputs. Output load is capacitive CONCORDIA VLSI DESIGN LAB PMOS Network Output Inputs NMOS Network 3 NAND Gates

Transistors in Parallel 1/Rcheff = (1/Rch1) + (1/Rch2) W ---L = W ----- + L 1 eff W ----- L 2 Transistors in Series (W/L)1 1 W 1 1 = W ----- + ----- L 1 L 2

eff CONCORDIA VLSI DESIGN LAB (W/L)eff (W/L)1 (W/L)eff Rcheff = Rch1 + Rch2 W ---L (W/L)2 (W/L)2 4 CMOS NAND Gate DC Analysis Two possible scenarios: 1. Both inputs are toggling

2. One input is toggling, the other one set high Assumptions: MP2=MP1=MP MN1=MN2=MN W/L for MP = (W/L)p W/L for MN = (W/L)n Inverter VTC CONCORDIA VLSI DESIGN LAB 5 Gate Sizing To obtain equal Rise and Fall time, Size the series / parallel transistors to have an equivalent of a single PU or PD inverter transistor in your design

CONCORDIA VLSI DESIGN LAB 6 Sizing the CMOS Gate CONCORDIA VLSI DESIGN LAB 7 NAND Gates: Analysis Scenario #1Both inputs are toggling L-H > (W/L)eff = 2(W/L)p H-L > (W/L)eff = 1/2(W/L)n KR|NAND = 1/4 KR|INV Scenario #2One input is toggling L-H > (W/L)eff = (W/L)p H-L > (W/L)eff = 1/2(W/L)n KR|NAND = 1/2 KR|INV CONCORDIA VLSI DESIGN LAB

Vin Inverter V OH One input toggling Two inputs toggling Vin=Vou t VOL Vx2 Vx1 Vout 8 NAND Gates: Analysis Switching Analysis VDD

Scenario #1Both inputs are toggling MP2 tPLH |NAND = 1/2tPLH |INVERTER tPHL |NAND = 2tPHL |INVERTER X A Scenario #2One input is toggling MP1 B MN1 CL MN2 tPLH |NAND = tPLH |INVERTER tPHL |NAND = 2tPHL |INVERTER

CONCORDIA VLSI DESIGN LAB 9 NAND Gate: Power Dissipation Pac= .f . C VDD2 A 0 1 0 1 B 0 0 1 1 X 1 1 1

0 VDD MP2 MP1 X A B MN1 CL MN2 = P (X=1). P (X=0) assuming A and B have equal probabilities for 1 and 0 = (1/4). (3/4)= 3/16 C = CL + C parasitic CONCORDIA VLSI DESIGN LAB

10 Increasing the inputs CONCORDIA VLSI DESIGN LAB 11 NOR Gate: Analysis DC Analysis/ AC Analysis Two possible scenarios: 1. Both inputs are toggling (one is set low) 2. One input is toggling, the other one set high Assumptions: AP2=BP1=MP AN1=BN2=MN W/L for MP = (W/L)p W/L for MN = (W/L)n Compare with a CMOS inverter: MP/MN KR, and the shift in VTC Propagation delay tPLH and tPHL CONCORDIA VLSI DESIGN LAB

12 4 INPUT NOR Gate VDD A Very slow rise time and rise delays Could be compensated by increasing of PMOS transistor size. Implications: Silicon Area Input capacitance C D X A CONCORDIA VLSI DESIGN LAB B

B C D CL 13 Practical Considerations 1. Minimize the use of NOR gates 2. Minimize the fan-in of NOR gates 3. Limit the fan-in to 4 for NAND gates 4. Use De morgans theorem to reduce the number of fan-in per gate Example: F = ABCDEFGH = (ABCD) + (EFGH) CONCORDIA VLSI DESIGN LAB 14 Complex CMOS Gate

CONCORDIA VLSI DESIGN LAB 15 Reducing Output Capacitance CONCORDIA VLSI DESIGN LAB 16 Pseudo nMOS CONCORDIA VLSI DESIGN LAB 17 Pseudo nMOS NAND/NOR Gates CONCORDIA VLSI DESIGN LAB

From Lecture #4 For acceptable operation WN=1.5 WP for our Process respecting min WP 18 Pseudo nMOS Complex Gates From Lecture #4 For acceptable operation WN=1.5 WP for our Process respecting min WP CONCORDIA VLSI DESIGN LAB 19 CASCODE LOGIC Lad is cross coupled pMOS transistors

Logic is series and parallel complementary transistors Input and Output are in Complementary CONCORDIA VLSI DESIGN LAB 20 CSACODE Inverter/Nand Gate CONCORDIA VLSI DESIGN LAB 21 CASCODE Complex Gate CONCORDIA VLSI DESIGN LAB

22 DCVS trees for a full adder Sum and Carry Pull-Down Networks CONCORDIA VLSI DESIGN LAB S(A,B,C) = ABC + ABC + ABC + ABC S (A,B,C) = ABC + ABC + ABC + ABC C(A,B,C) = AB + BC + AC 23 Transmission Gate Bi-directional switch, passes digital signals Less complex and more versatile than AND gate Passes analog signals A C B Problems: Large ON resistance during transitions of input signals

Large input and output capacitance (useful for data storage applications) A Capacitive coupling Applications: Multiplexers, encoders, latches, registers various combinational logic circuits A C C B C C C B A TG B

INV included CONCORDIA VLSI DESIGN LAB C 24 NMOS/PMOS as Pass Transistors NMOS Transistor C Vo VDD -VTN Passes weak 1 signal Vo = VDD -VTN Passes 0 signal undegraded Vi Vo

CL VDD -VTN Vi PMOS Transistor Vo C Passes 1 signal undegraded Vi -VTP Passes weak 0 signal Vo= -VTP CONCORDIA VLSI DESIGN LAB Vo CL

-VTP Vi 25 TX Gate: Characteristics Vo C Vo Vin Vin R nmos:lin nmos:sat pmos:sat pmos:lin 0V |VTP| CONCORDIA VLSI DESIGN LAB

VDD-VTN Req,p nmos:off pmos:lin VDD Req,n Req,TX 0 VDD-VTN VDD Vo 26 AND, NAND CONCORDIA VLSI DESIGN LAB

A B F 0 0 0 0 1 0 1 0 0 1

1 1 27 OR, NOR CONCORDIA VLSI DESIGN LAB A B F 0 0 0 0

1 1 1 0 1 1 1 1 28 A multiplexer CONCORDIA VLSI DESIGN LAB C

A B F C A B F 0 0 0 0 1

0 0 0 0 0 1 1 1 0 1 0 0 1

0 0 1 1 0 1 0 1 1 1 1 1

1 1 29 XOR CONCORDIA VLSI DESIGN LAB A B F 0 0 0 0

1 1 1 0 1 1 1 0 30 Four to one multiplexer CONCORDIA VLSI DESIGN LAB 31

TX Gate: Layout C P+ VDD P+ Vi VO N+ N+ C CONCORDIA VLSI DESIGN LAB VSS C C For data path structure 32

NAND Gates: Layout Layout Transistors in Series Transistors in Parallel CONCORDIA VLSI DESIGN LAB 33 NAND Gates: Layout VDD Via Metal II X A CONCORDIA VLSI DESIGN LAB B

GND 34 NOR Gate: Layout VDD X CONCORDIA VLSI DESIGN LAB B A GND 35 Analysis and Design of Complex Gate Analysis

p+ layer A B C D E F VDD 1. 2. 3. 4. Construct the schematic Determine the logic function. Determine transistor sizes. Determine the input pattern to cause slowest and fastest

contact operations. 5. Determine the worst case rise delay (tPLH)and fall delay (tPHL) 6. Determine the best case rise and fall delays. OUT N-well GND A n+ layer B polysilicon CONCORDIA VLSI DESIGN LAB C

D E metal F active (diffusion) 36

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