Scalable Vector Media-processors for Embedded DRAM

Scalable Vector Media-processors for Embedded DRAM

Lecture 15 Multimedia Instruction Sets: SIMD and Vector Christoforos E. Kozyrakis ([email protected]) CS252 Graduate Computer Architecture University of California at Berkeley March 14th, 2001 What is Multimedia Processing? CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Desktop: C.E. Kozyrakis, 3/14/01 3D graphics (games) Speech recognition (voice input) Video/audio decoding (mpeg-mp3 playback) Servers: Video/audio encoding (video servers, IP telephony) Digital libraries and media mining (video servers) Computer animation, 3D modeling & rendering (movies) Embedded:

3D graphics (game consoles) Video/audio decoding & encoding (set top boxes) Image processing (digital cameras) Signal processing (cellular phones) 2 The Need for Multimedia ISAs CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Why arent general-purpose processors and ISAs sufficient for multimedia (despite Moores law)? Performance A 1.2GHz Athlon can do MPEG-4 encoding at 6.4fps One 384Kbps W-CDMA channel requires 6.9 GOPS Power consumption A 1.2GHz Athlon consumes ~60W Power consumption increases with clock frequency and complexity Cost A 1.2GHz Athlon costs ~$62 to manufacture and has a

list price of ~$600 (module) Cost increases with complexity, area, transistor count, power, etc 3 Example: MPEG Decoding CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Input Stream Load Breakdown Parsing 10% Dequantization 20% IDCT 25% Block Reconstruction RGB->YUV 30% 15%

Output to Screen 4 Example: 3D Graphics CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Display Lists Geometry Pipe Transform Lighting Setup Load Breakdown 10% 10% Rasterization Anti-aliasing Rendering Pipe Shading, fogging 35%

Texture mapping Alpha blending Z-buffer 55% Clipping Frame-buffer Outputops to Screen 5 Characteristics of Multimedia Apps (1) CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Requirement for real-time response C.E. Kozyrakis, 3/14/01 Incorrect result often preferred to slow result Unpredictability can be bad (e.g. dynamic execution) Narrow data-types Typical width of data in memory: 8 to 16 bits Typical width of data during computation: 16 to 32 bits 64-bit data types rarely needed

Fixed-point arithmetic often replaces floating-point Fine-grain (data) parallelism Identical operation applied on streams of input data Branches have high predictability High instruction locality in small loops or kernels 6 Characteristics of Multimedia Apps (2) CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Coarse-grain parallelism C.E. Kozyrakis, 3/14/01 Most apps organized as a pipeline of functions Multiple threads of execution can be used Memory requirements High bandwidth requirements but can tolerate high latency High spatial locality (predictable pattern) but low temporal locality Cache bypassing and prefetching can be crucial 7 Examples of Media Functions CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector

Matrix transpose/multiply DCT/FFT Motion estimation Gamma correction Haar transform Median filter Separable convolution Viterbi decode Bit packing Galois-fields arithmetic C.E. Kozyrakis, 3/14/01 (3D graphics) (Video, audio, communications)

(Video) (3D graphics) (Media mining) (Image processing) (Image processing) (Communications, speech) (Communications, cryptography) (Communications, cryptography) 8 Approaches to Mediaprocessing CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 General-purpose Vector Processors processors with SIMD extensions VLIW with SIMD extensions (aka mediaprocessors) Multimedia

Processing DSPs ASICs/FPGAs 9 SIMD Extensions for GPP CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Motivation C.E. Kozyrakis, 3/14/01 Low media-processing performance of GPPs Cost and lack of flexibility of specialized ASICs for graphics/video Underutilized datapaths and registers Basic idea: sub-word parallelism Treat a 64-bit register as a vector of 2 32-bit or 4 16bit or 8 8-bit values (short vectors) Partition 64-bit datapaths to handle multiple narrow operations in parallel Initial constraints No additional architecture state (registers) No additional exceptions Minimum area overhead 10

Overview of SIMD Extensions CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Vendor Extension Year # Instr Registers HP MAX-1 and 2 94,95 9,8 (int) Int 32x64b Sun VIS 95 121 (int)

FP 32x64b Intel MMX 97 57 (int) FP 8x64b AMD 3DNow! 98 21 (fp) FP 8x64b Altivec 98 162 (int,fp) 32x128b (new)

Intel SSE 98 70 (fp) 8x128b (new) MIPS MIPS-3D ? 23 (fp) FP 32x64b AMD E 3DNow! 99 24 (fp) 8x128 (new) Intel

SSE-2 01 144 (int,fp) 8x128 (new) Motorola 11 Example of SIMD Operation (1) CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Sum of Partial Products * + * * *

+ 12 Example of SIMD Operation (2) CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Pack (Int16->Int8) 13 Summary of SIMD Operations (1) CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Integer arithmetic C.E. Kozyrakis, 3/14/01 Addition and subtraction with saturation

Fixed-point rounding modes for multiply and shift Sum of absolute differences Multiply-add, multiplication with reduction Min, max Floating-point arithmetic Packed floating-point operations Square root, reciprocal Exception masks Data communication Merge, insert, extract Pack, unpack (width conversion) Permute, shuffle 14 Summary of SIMD Operations (2) CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Comparisons C.E. Kozyrakis, 3/14/01 Integer and FP packed comparison Compare absolute values Element masks and bit vectors Memory No new load-store instructions for short vector

No support for strides or indexing Short vectors handled with 64b load and store instructions Pack, unpack, shift, rotate, shuffle to handle alignment of narrow data-types within a wider one Prefetch instructions for utilizing temporal locality 15 Programming with SIMD Extensions CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Optimized shared libraries C.E. Kozyrakis, 3/14/01 Written in assembly, distributed by vendor Need well defined API for data format and use Language macros for variables and operations C/C++ wrappers for short vector variables and function calls Allows instruction scheduling and register allocation optimizations for specific processors Lack of portability, non standard Compilers for SIMD extensions No commercially available compiler so far Problems Language support for expressing fixed-point arithmetic

and SIMD parallelism Complicated model for loading/storing vectors Frequent updates Assembly coding 16 SIMD Performance CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Speedup over Base Architecture for Berkeley Media Benchm arks Arithmetic Mean Geometic Mean 8 6 4 2 0 Athlon Alpha 21264

P entium III P owerP C G4 UltraSparc IIi Limitations Memory bandwidth Overhead of handling alignment and data width adjustments 17 A Closer Look at MMX/SSE Speedup over Base Architecture CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 PentiumIII (500MHz) with MMX/SSE 31.1 10 7.6 8 6.4 4.9 6

5.6 4 2 1.3 1.7 2.8 3.8 4.7 2 2.5 1.5 1.3 2.2 1.8 0 Higher speedup for kernels with narrow data where 128b SSE instructions can be used Lower speedup for those with irregular or strided accesses 18 CS 252 Administrivia CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector

No announcements for today C.E. Kozyrakis, 3/14/01 Chip design toys to see during break Wafers Packages Packaged chips Boards 19 Vector Processors CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Initially developed for super-computing applications, but we will focus only on multimedia today Vector processors have high-level operations that work on linear arrays of numbers: "vectors" VECTOR

SCALAR (N operations) (1 operation) r1 r2 v1 v2 + + r3 v3 add r3, r1, r2 vector length vadd.vv v3, v1, v2 20 Properties of Vector Processors CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Single vector instruction implies lots of work (loop)

Fewer instruction fetches Each result independent of previous result Compiler ensures no dependencies Multiple operations can be executed in parallel Simpler design, high clock rate Reduces branches and branch problems in pipelines Vector instructions access memory with known pattern Effective prefetching Amortize memory latency of over large number of elements Can exploit a high bandwidth memory system No (data) caches required! 21 Styles of Vector Architectures CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Memory-memory vector processors C.E. Kozyrakis, 3/14/01

All vector operations are memory to memory Vector-register processors All vector operations between vector registers (except vector load and store) Vector equivalent of load-store architectures Includes all vector machines since late 1980s We assume vector-register for rest of the lecture 22 Components of a Vector Processor CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Scalar CPU: registers, datapaths, instruction fetch logic Vector register Fixed length memory bank holding a single vector Has at least 2 read and 1 write ports Typically 8-32 vector registers, each holding 1 to 8 Kbits Can be viewed as array of 64b, 32b, 16b, or 8b elements Vector functional units (FUs) Fully pipelined, start new operation every clock Typically 2 to 8 FUs: integer and FP Multiple datapaths (pipelines) used for each unit to process multiple elements per cycle Vector load-store units (LSUs) Fully pipelined unit to load or store a vector

Multiple elements fetched/stored per cycle May have multiple LSUs Cross-bar to connect FUs , LSUs, registers 23 Basic Vector Instructions CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Instr. Operands Operation Comment VADD.VV V1,V2,V3 V1=V2+V3 vector + vector VADD.SV V1,R0,V2 V1=R0+V2 scalar + vector VMUL.VV V1,V2,V3 V1=V2xV3 vector x vector VMUL.SV V1,R0,V2 V1=R0xV2 scalar x vector VLD V1,R1 V1=M[R1..R1+63] load, stride=1 VLDS V1,R1,R2 V1=M[R1..R1+63*R2] load, stride=R2 VLDX

V1,R1,V2 V1=M[R1+V2i,i=0..63] indexed("gather") VST V1,R1 M[R1..R1+63]=V1 store, stride=1 VSTS V1,R1,R2 V1=M[R1..R1+63*R2] store, stride=R2 VSTX V1,R1,V2 V1=M[R1+V2i,i=0..63] indexed(scatter") + all the regular scalar instructions (RISC style) 24 Vector Memory Operations CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Load/store operations move groups of data between registers and memory Three types of addressing Unit stride Fastest Non-unit (constant) stride Indexed (gather-scatter) Vector equivalent of register indirect Good for sparse arrays of data

Increases number of programs that vectorize Support for various combinations of data widths in memory and registers {.L,.W,.H.,.B} x {64b, 32b, 16b, 8b} 25 Vector Code Example CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Y[0:63] = Y[0:653] + a*X[0:63] 64 element SAXPY: scalar loop: LD ADDI LD MULTD LD ADDD SD ADDI ADDI SUB BNZ R0,a

R4,Rx,#512 R2, 0(Rx) R2,R0,R2 R4, 0(Ry) R4,R2,R4 R4, 0(Ry) Rx,Rx,#8 Ry,Ry,#8 R20,R4,Rx R20,loop 64 element SAXPY: vector LD R0,a #load scalar a VLD V1,Rx #load vector X VMUL.SV V2,R0,V1 #vector mult VLD V3,Ry #load vector Y

VADD.VV V4,V2,V3 #vector add VST Ry,V4 #store vector Y 26 Setting the Vector Length CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 A vector register can hold some maximum number of elements for each data width (maximum vector length or MVL) What to do when the application vector length is not exactly MVL? Vector-length (VL) register controls the length of any vector operation, including a vector load or store E.g. vadd.vv with VL=10 is for (I=0; I<10; I++) V1[I]=V2[I]+V3[I] VL can be anything from 0 to MVL How do you code an application where the vector length is not known until run-time? 27

Strip Mining CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Suppose application vector length > MVL Strip mining C.E. Kozyrakis, 3/14/01 Generation of a loop that handles MVL elements per iteration A set operations on MVL elements is translated to a single vector instruction Example: vector saxpy of N elements First loop handles (N mod MVL) elements, the rest handle MVL VL = (N mod MVL); for (I=0; I

28 Choosing the Data Type Width CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Alternatives for selecting the width of elements in a vector register (64b, 32b, 16b, 8b) Separate instructions for each width E.g. vadd64, vadd32, vadd16, vadd8 Popular with SIMD extensions for GPPs Uses too many opcodes Specify it in a control register Virtual-processor width (VPW) Updated only on width changes NOTE MVL increases when width (VPW) gets narrower E.g. with 2Kbits for register, MVL is 32,64,128,256 for 64-,32-,16-,8-bit data respectively Always pick the narrowest VPW needed by the application 29 Other Features for Multimedia CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector

Support for fixed-point arithmetic C.E. Kozyrakis, 3/14/01 Saturation, rounding-modes etc Permutation instructions of vector registers For reductions and FFTs Not general permutations (too expensive) Example: permutation for reductions Move 2nd half a a vector register into another one Repeatedly use with vadd to execute reduction Vector length halved after each step 0 1 5 1 6 6 3 0 1 5

1 6 6 3 V0 V1 30 Optimization 1: Chaining CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Suppose: vmul.vv vadd.vv V1,V2,V3 V4,V1,V5 # RAW hazard Chaining Vector register (V1) is not as a single entity but as a group of individual registers

Pipeline forwarding can work on individual vector elements Flexible chaining: allow vector to chain to any other active vector operation => more Unchained read/write ports vmul Chained vadd vmul vadd 31 Optimization 2: Multi-lane Implementation CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Pipelined Lane Datapath

Vector Reg. Partition Functional Unit To/From Memory System Elements for vector registers interleaved across the lanes Each lane receives identical control Multiple element operations executed per cycle Modular, scalable design No need for inter-lane communication for most vector instructions 32 Chaining & Multi-lane Example CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Scalar C.E. Kozyrakis, 3/14/01

LSU FU0 FU1 vld vmul.vv vadd.vv addu Time vld vmul.vv vadd.vv addu Element Operations: Instr. Issue: VL=16, 4 lanes, 2 FUs, 1 LSU, chaining -> 12 ops/cycle Just one new instruction issued per cycle !!!! 33 Optimization 3: Conditional Execution CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Suppose you want to vectorize this:

C.E. Kozyrakis, 3/14/01 for (I=0; I

Ra 34 Vector Architecture State CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Virtual Processors ($mvl) VP0 General Purpose Registers VP1 VP$mvl-1 vr0 vr1 Scalar Registers vr31 $vpw bits Flag Registers

(32) r0 r1 vf0 vf1 r31 64 bits vf31 1 bit 35 Two Ways to Vectorization CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Inner loop vectorization C.E. Kozyrakis, 3/14/01 Think of machine as, say, 32 vector registers each with 16 elements 1 instruction updates 32 elements of 1 vector register Good for vectorizing single-dimension arrays or regular kernels (e.g. saxpy) Outer loop vectorization Think of machine as 16 virtual processors (VPs)

each with 32 scalar registers! ( multithreaded processor) 1 instruction updates 1 scalar register in 16 VPs Good for irregular kernels or kernels with loop-carried dependences in the inner loop These are just two compiler perspectives The hardware is the same for both 36 Outer-loop Example (1) CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 // Matrix-matrix multiply: // sum a[i][t] * b[t][j] to get c[i][j] for (i=1; i

} 37 Outer-loop Example (2) CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 // Outer-loop Matrix-matrix multiply: // sum a[i][t] * b[t][j] to get c[i][j] // 32 elements of the result calculated in parallel // with each iteration of the j-loop (c[i][j:j+31]) for (i=1; i

c[i][j:j+31] = sum[0:31]; // vector store } 38 Designing a Vector Processor CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Changes to scalar core How to pick the maximum vector length? How to pick the number of vector registers? Context switch overhead? Exception handling? Masking and flag instructions? 39 Changes to Scalar Processor

CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Decode vector instructions Send scalar registers to vector unit (vector-scalar ops) Synchronization for results back from vector register, including exceptions Things that dont run in vector dont have high ILP, so can make scalar CPU simple 40 How to Pick Max. Vector Length? CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Vector length => Keep all VFUs busy: C.E. Kozyrakis, 3/14/01 (# lanes) X (# VFUs ) Vector length >= # Vector instr. issued/cycle Notes: Single instruction issue is always the simplest Dont forget you have to issue some scalar instructions as well

41 How to Pick Max Vector Length? CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Longer good because: C.E. Kozyrakis, 3/14/01 Lower instruction bandwidth If know max length of app. is < max vector length, no strip mining overhead Tiled access to memory reduce scalar processor memory bandwidth needs Better spatial locality for memory access Longer not much help because: Diminishing returns on overhead savings as keep doubling number of elements Need natural app. vector length to match physical register length, or no help Area for multi-ported register file 42 How to Pick # of Vector Registers? CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector

More vector registers: C.E. Kozyrakis, 3/14/01 Reduces vector register spills (save/restore) Aggressive scheduling of vector instructions: better compiling to take advantage of ILP Fewer Fewer bits in instruction format (usually 3 fields) 32 vector registers are usually enough 43 Context Switch Overhead? CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 The vector register file holds a huge amount of architectural state To expensive to save and restore all on each context switch Extra dirty bit per processor If vector registers not written, dont need to save on context switch

Extra valid bit per vector register, cleared on process start Dont need to restore on context switch until needed Extra tip: Save/restore vector state only if the new context needs to issue vector instructions 44 Exception Handling: Arithmetic CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Arithmetic traps are hard Precise interrupts => large performance loss Multimedia applications dont care much about arithmetic traps anyway Alternative model Store exception information in vector flag registers A set flag bit indicates that the corresponding element operation caused an exception Software inserts trap barrier instructions from SW to check the flag bits as needed IEEE floating point requires 5 flag registers (5 types of traps)

45 Exception Handling: Page Faults CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Page faults must be precise C.E. Kozyrakis, 3/14/01 Instruction page faults not a problem Data page faults harder Option 1: Save/restore internal vector unit state Freeze pipeline, (dump all vector state), fix fault, (restore state and) continue vector pipeline Option 2: expand memory pipeline to check all addresses before send to memory Requires address and instruction buffers to avoid stalls during address checks On a page-fault on only needs to save state in those buffers Instructions that have cleared the buffer can be allowed to complete 46 Exception Handling:

Interrupts CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Interrupts due to external sources C.E. Kozyrakis, 3/14/01 I/O, timers etc Handled by the scalar core Should the vector unit be interrupted? Not immediately (no context switch) Only if it causes an exception or the interrupt handler needs to execute a vector instruction 47 Vector Power Consumption CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Can trade-off parallelism for power C.E. Kozyrakis, 3/14/01 Power = C *Vdd2 *f If we double the lanes, peak performance doubles Halving f restores peak performance but also allows halving of the Vdd Powernew = (2C)*(Vdd/2)2*(f/2) = Power/4

Simpler logic Replicated control for all lanes No multiple issue or dynamic execution logic Simpler to gate clocks Each vector instruction explicitly describes all the resources it needs for a number of cycles Conditional execution leads to further savings 48 Why Vectors for Multimedia? CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Natural match to parallelism in multimedia C.E. Kozyrakis, 3/14/01 Vector operations with VL the image or frame width Easy to efficiently support vectors of narrow data types High performance at low cost Multiple ops/cycle while issuing 1 instr/cycle Multiple ops/cycle at low power consumption Structured access pattern for registers and memory Scalable Get higher performance by adding lanes without architecture modifications

Compact code size Describe N operations with 1 short instruction (v. VLIW) Predictable performance No need for caches, no dynamic execution Mature, developed compiler technology 49 Comparison with SIMD CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector More scalable C.E. Kozyrakis, 3/14/01 Can use double the amount of HW (datapaths/registers) without modifying the architecture or increasing instruction issue bandwidth Simpler hardware A simple scalar core is enough Multiple operations per instruction Full support for vector loads and stores No overhead for alignment or data width mismatch Mature compiler technology Although language problems are similar

Disadvantages Complexity of exception model Out of fashion 50 A Vector Media-Processor: VIRAM CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 Technology: IBM SA-27E 0.18mm CMOS, 6 copper layers 280 mm2 die area 158 mm2 DRAM, 50 mm2 logic Transistor count: ~115M 14 Mbytes DRAM Power supply & consumption 1.2V for logic, 1.8V for DRAM 2W at 1.2V Peak performance 1.6/3.2 /6.4 Gops (64/32/16b ops) 3.2/6.4/12.8 Gops (with madd) 1.6 Gflops (single-precision)

Designed by 5 graduate students 51 Performance Comparison CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 VIRAM MMX iDCT 0.75 3.75 (5.0x) Color Conversion 0.78 8.00 (10.2x) Image Convolution 1.23 5.49 (4.5x)

QCIF (176x144) 7.1M 33M (4.6x) CIF (352x288) 28M 140M (5.0x) QCIF and CIF numbers are in clock cycles per frame All other numbers are in clock cycles per pixel MMX results assume no first level cache misses 52 FFT (1) CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01 FFT (Floating-point, 1024 points) 160 Execution Time (usec) 124.3 120

VIRAM 92 80 40 69 Pathfinder-2 Wildstar TigerSHARC ADSP-21160 36 16.8 25 TMS320C6701 0 53 FFT (2) CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector C.E. Kozyrakis, 3/14/01

FFT (Fixed-point, 256 points) 151 Execution Time (usec) 160 120 VIRAM 87 80 Pathfinder-1 Carmel TigerSHARC PPC 604E Pentium 40 7.2 8.1 9 7.3 0

54 SIMD Summary CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector Narrow vector extensions for GPPs C.E. Kozyrakis, 3/14/01 64b or 128b registers as vectors of 32b, 16b, and 8b elements Based on sub-word parallelism and partitioned datapaths Instructions Packed fixed- and floating-point, multiply-add, reductions Pack, unpack, permutations Limited memory support 2x to 4x performance improvement over base architecture Limited by memory bandwidth Difficult to use (no compilers) 55 Vector Summary CS252, Lecture 15: Multimedia Instruction Sets: SIMD and Vector

C.E. Kozyrakis, 3/14/01 Alternative model for explicitly expressing data parallelism If code is vectorizable, then simpler hardware, more power efficient, and better real-time model than out-of-order machines with SIMD support Design issues include number of lanes, number of functional units, number of vector registers, length of vector registers, exception handling, conditional operations Will multimedia popularity revive vector architectures? 56

Recently Viewed Presentations

  • Research and Development Committee 1st June 2011

    Research and Development Committee 1st June 2011

    Research and Development Committee 1st June 2011 Review of Public Conveniences Julia Beckett DCE Brendan Coleman Head of Environmental Services Financial Context Budget Delivery framework Savings target 2011/12 = £1,900,000 Significant progress being made We still have a long way...
  • Presented by: Maria Petix Kent Environmental Specialist 3

    Presented by: Maria Petix Kent Environmental Specialist 3

    VSQ Generator PLANNED EVENT. Mario's Auto Body Planned and Prepared for: short-term project. removal of excess chemical inventory. cleanout of storage room chemicals, garage & tool shed cleanout, basements, and other areas at facility containing solvent-based paints & other hazardous...
  • Comma Splices and Run-on Sentences

    Comma Splices and Run-on Sentences

    A run-on is not a long sentence. Both the run-on and the comma splice can be two short sentences. A run-on/fused sentence, really two sentences without any punctuation, or conjunction between them, is identical to a comma splice but without...
  • How to Complete a Payment Information Form

    How to Complete a Payment Information Form

    Automated Clearing House (ACH) Vendor Payment Form. ACH Form Requirements. Effective March 1, 2013: As part of the OWCPs compliance with federal regulation 31 C.F.R Part 208, all providers that enroll in a U.S. Department of Labor Office of Workers'...
  • WELCOME TO ECONOMICS AND SOCIOLOGY DEPARTMENT Introduction Economics

    WELCOME TO ECONOMICS AND SOCIOLOGY DEPARTMENT Introduction Economics

    Economics comes from the Greek word Oikonomia. - Oikos(means a household) + Nomos(means management). So, it means household management. Aristotle. described economics as a household management that means the problems of food, shelter, clothing, education, treatment etc. for family members...
  • ERCOT Financial Summary For the Period Ending August

    ERCOT Financial Summary For the Period Ending August

    ERCOT Financial Summary For the Period Ending August 31, 2004 Board of Directors Meeting September 21, 2004 FY 2004 Results (Income Statement) 2004 Forecast 2004 Forecast Reasons for Lower Capital Spend in 2004 Reduced Scope by Market on Competitive Metering,...
  • Atrial Fibrilation Care Pathway Aug 10 - Wandsworth CCG

    Atrial Fibrilation Care Pathway Aug 10 - Wandsworth CCG

    If in doubt or symptoms persist consider cardiology referral or to ACC for reassurance. 2) 'Amber' patients - first line treatment should be considered in primary care. 2i)In cases of SCD in those <35yrs, screening of family members is indicated....
  • Extending Oblivious Transfers Efficiently Yuval Ishai Technion Joe

    Extending Oblivious Transfers Efficiently Yuval Ishai Technion Joe

    Since OT implies key exchange, it must be at least as expensive and its implementations involve costly operations such as modular exponentiations. As a result, OT's form the efficiency bottlneck in most protocols where they are used, and counting oblivious...