RISC Architecture - Pcpolytechnic

RISC Architecture - Pcpolytechnic

RISC Architecture Marks 18 Visit for more Learning Resources Basic Features of RISC Processor RISC (Reduced Instruction Set Computer) is a type of microprocessor architecture that utilizes a small, highly- optimized set of instructions, rather than a more specialized set of instructions often found in other types of architectures. 1. Simple Instruction Set: In RISC machines, the

instruction set contains simple basic instructions can be composed. These instructions with less latency are proffered. 2. Same length Instruction: each instruction is f same length, so that it may be fetched in single operation. The traditional microprocessors from intel or Motorola support variable length instructions. 3. Single Machine Cycle: Most instructions complete in one machine cycle, which allows the processor to handle several instructions at a same time. RISC processors have unity CPI (Clock per instruction),

which is due to optimization of each instruction on the CPU and pipelining is embedded in RISC processor. 4. Pipelining: Usually massive pipelining is embedded in a RISC. The pipelining is key to speed up RISC machine. 5. Very few address modes and format: Unlike the CISC processors, where the number of addressing modes are very high. In RISC processors the addressing modes are much less and it supports few formats.

6. Large number of Registers: the RISC design philosophy generally incorporates a large number of registers to prevent in large amount of interactions with memory. 7. Micro-Coding is not require: Unlike in SISC machine, in RISC architecture, instruction microcoding is not required. This is because of the availability of a set of simple instructions and simple instructions may be easily built into hardware. 8. Load and Store architecture: the RISC arch. Is primarily a LOAD and STORE archit., implying

that all the memory accesses take place using Load and Store type operation. Advantages of RISC Processor Higher- level language compilers are used to generate more efficient code as used the smaller set of instructions which is found in a RISC computer. Superscalar RISC processor gives 2-4 times the better performance as compare to CISC processors with the same clock rates as a simplified instruction set allows a pipelined. The instruction set of RISC processor requires much

less chip space for additional functions, such as MMU. Smaller chips size give a processor manufacturer to integrate more functional parts on single silicon chip, which will lower the per-chip cost. All instructions are executed in a single cycle hence have a faster execution time. Hybrid Architecture-RISC & SISC From last 30 years, there was a debate on the two basics

microprocessors architecture designs i.e. CISC and RISC architecture to decide which one is better for processor. Now a day, processor has been launched which causes the combination of CISC and RISC architectures. But practically, the processor designs use the only best features of RISC & SISC archt. And mix them in a hybrid Micro-architecture. CISC architecture have low burden on compiler developers and wide availability of existing software hence one group of designer supported CISC designs. RISC architecture has its simplicity and efficiency hence another group of designer supported RISC Designs.

But now a days, the processor designers realize that RISC designs migght benefit from the additiion of some CISC feature and vice-versa. Now a day, most of the CISC processor are based on Hybrid. i.e. CISC and RISC architecture. The Hybrid i.e. CISC and RISC architecture uses decoder which convert CISC instructions into RISC instructions proir execution and then they are processed by a RISC core, which performs a few basic instructions very fast. RISC architecture is better as it has performance enhancing features, such as pipelining and branch prediction.

The most popular hybrid processors are Pentium ans AMD Athlon family processors which are compatible with software written for their CISC predecessors. Now a days, modern RISC processors have become more CISC-like by supporting more functions and support more instructions than old CISC designs. By using the CISC architecture having more instructions, some applications may be run much faster such as multimedia applications, such

as telecommunications encoding/decoding, image conversions and video processing. Features of SUN Ultra SPARC The ULTRA SPARC means Scalable Processor ARChitecture is a processor developed by Sun Microsystems The Ultra SPARC is a four superscalar microprocessor that has a nine stage integer pipeline. The Ultra SPARC has two levels of cache i.e. Primary and Secondary. There are two Primary caches, one for instructions and one for data and both are 16KB

in capacity. Superscalar CPU where more than one instruction can be issued at a time for execution and Nine stage pipeline, issuing up to 4 instructions per cycle to minimize latency. Only simple Load/Store to memory i.e. load/store floating point quad- word instructions which load and store 128 bits at a time. Integer Unit(IU), Floating point Unit (FPU), Coprocessor CP) has its own register set, which allows maximum concurrency between integer, floating point and coprocessor instructions. Support up to 128 general purpose registers and all IU &

FPU registers are 32 bits wide. Separate instruction-TLB and Data-TLB, each has 64 entries. On-chip memory management Unit(MMU) gives memory protection where any process can be prohibited from reading or writing the address space of another process. For more detail contact us

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