Ramon Chips RadSafe and J2K - European Space Agency

Ramon Chips RadSafe and J2K - European Space Agency

Ramon Chips Ramon Chips is named in memory of Col. Ilan Ramon, Israeli astronaut who died on board the Columbia space shuttle, 1/2/2003 Rad-Tolerant design of all-digital DLL Tuvia Liran [[email protected] ] Ran Ginosar [[email protected] ] Dov Alon [[email protected] ] Ramon-Chips Ltd., Israel Ramon Outline Issues with analog DLL/PLL All-digital DLL (ADDLL) architecture Radiation hardening of ADDLL Applications of ADDLL Integration of ADDLL in SOC Future developments Ramon 2

Issues with analog PLL frequency Ionizing particle clk_ref PFD + CP VCO clk_out control voltage control voltage /N Issues: - Sensitive to TID of analog - Might un-lock due to SET - Accumulate phase error due to

SET - Might miss cycle due to SET - Sensitive to process, voltage, temperature Discharge by ionizing particle time frequency phase time Missing clock cycle time Ramon 3 All-digital DLL concept Standard cell based logic Operates at wide range of process, voltage & temperature Timing is controlled by logic

Fast locking / immediate re-locking Low jitter typically <1% of CLKREF period DCDL MUL CLK1X CLK2X CLK4X ctrl[m-1:0] REFCLK PHD up dn CTRL clkfb Ramon 4

DCDL operation IN EN0 EN1 EN2 OUT Gross tuning of delay Fine tuning of delay Ramon 5 DCDL response to control code DCDL4 Delay vs code 1.40E-08 1.20E-08

1.00E-08 Delay 8.00E-09 6.00E-09 4.00E-09 2.00E-09 0.00E+00 0 50 100 150 200 250 300

350 400 450 Code slow typ Ramon fast up_slow up_fast dn_slow dn_fast 6 Radiation hardening of

ADDLL Key radiation hazards: TID SEL Phase error due to SE Clock spike due to SET Reset/re-configure due to SEU/SET RH mitigation techniques The use of RadSafeTM std. cells immunity to TID & SEL Use of SEP flip-flops mitigates SEU immunity to change in control Glitch filtering at each DCDL stage mitigates SET spikes Requirements for double sampling of reset mitigates SET in reset/load Ramon 7

Advantages of ADDLL Voltage range as logic core Temperature range as logic core Lock time limited # of cycles Re-locking time immediate Standby power zero Dynamic power very low Bursts of clocks - enabled Control of slave delay lines - enabled Area very small Floor planning anywhere in the chip / I/O strip Immunity to Soft-Errors - Optional

Ramon 8 ADDLL in RadSafeTM library CTRLEN FBCLK PHDREF PHD Phase detector BCNT[11:0] CTRL_IN[11:0] DLCTR Delay controller LDEN LDB CLKOUT REFCLK

DCDL Digitally Controlled Delay Line PH[8:1] CLK1X CLK2X CLK4X DCDLEN Ramon FCLKEN 9 All-digital DLL cores Three DLL cores for 3 frequency ranges Locking guaranteed 0.05 mm2/core 8 mW/core @0.18u Highly protected from radiation effects Can be placed anywhere in the core Powered by core supply lines

Ramon 10 ADDLL application deskewing FBCLK CLKOUT PHDREF REFCLK CLK Tree ADDLL DCDLREF Ramon 11 ADDLL application frequency multiplication R E F C L K P H O U T [0 ]

P H O U T [1 ] P H O U T [2 ] P H O U T [3 ] P H O U T [4 ] P H O U T [5 ] P H O U T [6 ] P H O U T [7 ] C L K 2X C L K 4X Ramon 12 ADDLL application master-slave operation LO CK CTRLSL C TRL_O U T C T R L _ IN FBCLK LO CK


Ramon C LKO U T ADDLL P H O U T [n -1 :0 ] D CD LR EF RSTB C TR LEN DCDLEN P H O U T [2 n -1 :n ] 13 Other optional applications Frequency multiplication by 8X/16X Frequency multiplication by non 2n Duty cycle re-construction Digitally monitoring of aging/PVT Operation with bursts of clocks Frequency hoping

Ramon 14 Record of integrating ADDLLs Ramon 15 Example of ADDLL (commercial IP) Slave DCDL Slave CTRL PHD SYNC DCDL 80 Dig I/F

CTRL 140 TSMC/0.13u process Power: 2mW @1.2V 200-500MHz input clock Located inside I/O ring Area: 0.01mm2 DDR2 application Ramon 16 Summary ADDLL provides significant advantages over analog PLL/DLLs RH ADDLL overcomes the sensitivities of analog PLLs/DLLs ADDLL can be used for clock de-skewing and multiplication, and other applications RadSafeTM ADDLL is mature and proven Ramon 17

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