CMPE 450/490 ARM AT91EB55 Development Board & ATMEL

CMPE 450/490 ARM AT91EB55 Development Board & ATMEL

CMPE 450/490 ARM AT91EB55 Development Board & ATMEL AT91M55800A ARM7TDMI 2010 Elliott, Durdle, Minderman Portions courtesy of ARM, Atmel, Greenhill Overview The AT91EB55 board contains: An ATMEL AT91M55800A ARM7TDMI microcontroller 2M bytes of 16-bit Flash of which 1 MB is available for user software 256K byte of 16-bit SRAM upgradable to 1 MB 4M bytes of Serial Data Flash upgradeable to 16 MB

Two serial ports Eight LEDs Four user-defined push buttons Reset push button 20-pin JTAG interface connector 3 x 32 pin I/O expansion connector 2 x 32 pin EBI expansion connector 2 The AT91EB55 Board Layout

3 AT91EB55 Block Diagram 4 Testing the AT91EB55 Evaluation Board 1. To test the AT91EB55 Evaluation board, hold down the SW1 button and power up the board or generate a reset and wait for the light sequence on each LED to complete. 2. All the LEDs light once and the D1 LED remains lit. Release the SW1 button.

The LEDs D1 to D7 light up in sequential order. If an error is detected, all the LEDs will light up twice. The LEDs represent the following devices: D1 for the internal SRAM D2 for the external SRAM D3 for the external Flash D4 reserved D5 for the SPI data flash D6 reserved

D7 for the USART D8 for the ADC and DAC 5 On Board Software The 2MB AT49BV162A Flash ROM contains with the following software. The Boot Software Program (boot) The Functional Test Software (FTS) The Angel Debug Monitor A Default User Boot with a Default Application Only the lowest eight 8-Kbyte sectors are used. The remaining sectors are user-definable and can be programmed using one of the Flash downloader solutions offered in the AT91 library

The boot and FTS and are in sectors 0 and 1 of the Flash when delivered These sectors are not locked for an easy on-board upgrade. The user must avoid overwriting this sector. 6 The Boot Program The Boot Software Program configures the AT91M55800A It thus controls the memory and other board devices. The Boot Program is started at reset if JP1 is in the STD position. If JP1 is in the USER position the AT91M55800A boots from address 0x01010000 in the Flash, which must have a user-defined boot.

The Boot Program Initializes the master clock frequency at 32 MHz Configures the EBI Executes the REMAP Checks the state of the buttons As long as the SW1 button is pressed, all the LEDs light together The D1 LED remains lit until SW1 is released The Functional Test Software (FTS) is then started When the SW4 button is pressed the shutdown function from AT91M55800A is activated. When no buttons are pressed, branch to address 0x01006000 The Angel Debug Monitor starts from this address by recopying itself in external SRAM 7

Default Memory Map Part Name Start Address End Address Size Device

U1 0x1000000 0x011FFFFF 2-Mbyte Flash ROM U2-U3 0x02000000 0x0203FFFF 256-Kbyte SRAM

The Boot Program and FTS and are in sectors 0 and 1 of the Flash device Sectors 3 to 7 support the Angel Debug Monitor Sector 24 at address 0x01100000 must be programmed with a boot sequence to be debugged. This sector can be mapped at address 0x01000000 (or 0x0 after a reset) when the jumper JP1 is in the USER position. 8 Default Memory Map (continued) 9 The Angel Debug Monitor The Angel Debug Monitor is located in the Flash ROM from 0x01006000 up to 0x0100FFFF The boot program starts it if no button is pressed.

When Angel starts, it recopies itself in SRAM in order to run faster. The SRAM used by Angel is from 0x02020000 to 0x0203FFFF, i.e., the highest half part of the SRAM. The Angel on the AT91EB55 can be upgraded regardless of the version programmed on it. Note: If the debugger is started through ICE while the Angel monitor is on, the Advanced Interrupt Controller (AIC) and the USART channel are enabled. 10 AT915800 Embedded Peripherals I AT915800 Peripherals 12

SYSTEM and USER PERIPHERALS Overview System Peripherals External Bus Interface Advanced Interrupt Controller

Parallel I/O Controller Watchdog Peripheral Data Controller System Timer Power Management Controller Real Time Clock User Peripherals USART Serial Peripheral Interface Timer Counter Analog to Digital Converter Digital to Analog Converter

13 PIO Controller : Features Up to 58 Programmable Input Output lines I/O lines may be multiplexed with an on-chip peripheral signal to optimize the use of available package pins managed by the PIO controller Input Change Detection Interrupt on each line Available even in Peripheral mode Multi Driver (Open-Drain) Allows multiple devices to drive the PIO lines Reset state : all PIO configured as PIO in input PIO Multiplexed with EBI signals do not respect this rule 14 PIO Controller : Block Diagram

15 PIO Controller : I/O Levels Each pin can be configured to be driven high or low The level is defined in four different ways, according to the following conditions : If a pin is controlled by the PIO Controller and is not defined as an output, the level is determined by the external circuit. If a pin is controlled by the PIO Controller and is defined as an output, the level is programmed using the registers Set Output Data (PIO_SODR) and Clear Output Data (PIO_CODR). If a pin is not controlled by the PIO Controller, the state of the pin is defined by the peripheral. In all cases, the level on the pin can be read in the register PIO_PDSR (Pin Data Status). 16 AIC : Features

8-level Priority Up to 32 Interrupt sources Individually maskable Hardware interrupt vectoring Internal Interrupt sources

Level sensitive or edge triggered External Interrupt sources Low/High level sensitive or positive/negative edge triggered 17 AIC : Block Diagram 18 WatchDog : Features 16-bit Down Counter Programmable Time-out Period 4ms to 8s, with 33MHz system clock 4 Clock divide down options

MCK/32, MCK/128, MCK/1024 and MCK/4096 3 Independent Outputs Internal Reset Internal Interrupt Low level on Watchdog overflow signal for a duration of 8 MCK cycles Control access keys prevent writes, corruption 19 Watchdog : Block Diagram 20 System Timer : Features One Period Interval Timer (PIT) 16-bit programmable counter

periodic interrupt, useful for OS, e.g. time slicing One Watchdog Timer (WD) 16-bit programmable counter maximum watchdog period of 256s with a typical slow clock of 32.768kHz One Real Time Timer (RTT) 20-bit free-running counter count elapsed seconds 1s increment with a typical slow clock of 32.768kHz count up to 1048576s (12 days) Alarm to generate an interrupt

22 ST : Block Diagram 23 Timer Counter : Features Three 16-bit Timer/Counter channels Wide range of functions: Frequency measurement Event counting Interval measurement

Pulse generation Delay timing Pulse Width Modulation Clock inputs 3 External and 5 Internal Two configurable Input/Output signals Internal interrupt signal 24 TC : Block Diagram 25 TC : Clock Selection

Internal clock signals: MCK/2, MCK/8, MCK/32, MCK/128, MCK/1024 External clock signals: XC0, XC1, XC2 Selected clock can be inverted Burst Function 26 TC : Clock Control Counter clock can be enabled/disabled and started/stopped Software Enabling Commands by Control Register : CLKEN and CLKDIS Loading RB in Capture Mode or RC Compare in Waveform Mode can stop or disable the counter clock

27 TC : Operating Modes Two different modes: Capture Mode allows measurement on signals, Waveform Mode allows wave generation. Timer Counter Mode programmed with the WAVE bit in the TC Mode Register. 28 TC : Triggers A trigger resets the counter and starts the counter clock. The following triggers are common to both modes: Software Trigger Each channel has a software trigger, available by setting SWTRG in TC_CCR.

SYNC Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set. Compare RC Trigger RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. External triggers: TIOA or TIOB in Capture Mode TIOB, XC0,XCC1 or XC2 in Waveform Mode 29 TC : Capture Mode (1/3) Selected Clock

Capture Register A Capture Register B Register C 16-bit Counter RC Compare SYNC CPCTRG SWTRG TIOB

input TIOA input LDRA ABETRG Edge Detector RA Loading Logic LDRB RB Loading

Logic ETRGEDG TIOA and TIOB as input pins RA Loading Logic : can be loaded only after a trigger or if RB has been loaded RB Loading Logic : can be loaded only after a trigger and if RA has been loaded 30 TC : Capture Mode (2/3) Examples: Measure the phase between TIOB and TIOA and the duration of the TIOA pulse TIOB rising edge resets and starts the counter TIOA rising edge loads RA and a falling edge loads RB

RA contains the phase between TIOB and TIOA (RB-RA) is the duration of the TIOA pulse 31 TC : Capture Mode (3/3) Measure the duration of a TIOA pulse or period TIOA falling edge resets and starts the counter and loads RB if RA is already loaded TIOA rising edge loads RA RA contains the duration of a TIOA pulse (low level) RB contains the duration of the TIOA period 32 TC : Waveform Mode (1/2) Selected Clock

Register C RA Compare RB Compare RC Compare ASWTRG CPCTRG SWTRG ENETRG EEVT TIOB input

Register B 16-bit Counter SYNC XC0 XC1 XC2 Register A AEEVT ACPC ACPA TIOA output

BSWTRG Edge Detector EEVTEDG BEEVT BCPC BCPB TIOB output TIOA is an output TIOB can be input or output depending on EEVT programming ( default is input ) Output controllers can set, clear or toggle outputs in function of events 33 TC : Waveform Mode (2/2)

Examples: Dual Pulse Width Modulation (PWM) generation TIOA is toggled by RA and RC, TIOB by RB and RC A trigger starts the counter and initializes TIOA and TIOB The PWM frequency must be stored in the compare register RC The duty cycles on TIOA and TIOB are defined by RA and RB respectively 34 USART : Features Programmable Baud Rate Generator with External or Internal Clock Up to 1Mbits/s in Asynchronous Mode and up to 16Mbits/s in Synchronous Mode at 32MHz Parity, Framing and Overrun Error Detection Line Break generation and detection Automatic Echo, Local Loopback and Loopback Channel Modes

Multi Drop Mode : Address Detection and Generation Interrupt Generation 2 Dedicated PDC Channels 5,6,7,8 and 9-bit Character Length Transmitter Time Guard 35 USART : Block Diagram 36 USART : Baud Rate Generator Asynchronous Mode Baud rate = MCK period / 16 / CD Synchronous Mode Baud Rate = MCK period /

CD 37 USART : Reception Asynchronous: 8 bit 1 start and 1 stop D0 D1 D2 D3 D4 D5 D6

Next D7 Start Stop SCK Synchronous: 8 bit 1 start and 1 stop RXD TXD D0 Start

D1 D2 D3 D4 D5 D6 Next D7 Stop 38

USART : Transmission Asynchronous and Synchronous : 8 bit, parity and 1 stop 39 USART : PDC Channels PDC shares the ASB bus with the ARM Core External or Internal Memories Access ARM Core stopped during 3 cycles min. PDC Channel ARM Core

ASB Arbiter Each PDC channel is dedicated to a peripheral and a transfer direction PDC Registers mapped in User Interface End of Transfer in the Status Register Typical Application Code download Packet Exchange RXRDY RXEND Size = Byte

USART TXRDY TXEND Size = Byte PDC Receive Channel PDC Transmit Channel Receiver Timeout Helps to Support Variable Length Packets Transmitter Time Guard helps to Support Slow Remote Devices

40 SPI : Features Serial Interface between CPU and External Peripherals Master or Slave Mode Full duplex 3 wires synchronous transfer MISO: Master In Slave Out MOSI: Master Out Slave In SPCK: SPI Clock Maximum SPI baud rate clock: MCK/4 4 External Slave chip selects 8 to 16-bit Programmable Data Length

Mode Fault Detection in Master Mode 2 Dedicated PDC Channels 41 SPI Timing (example) 42 SPI : Block Diagram 43 SPI : Bus Implementations Up to 4 Peripherals Up to 15 Peripherals with Decoding AT91

AT91 SPI SPI NPCS3 NPCS2 NPCS1 NPCS0 4 to 16 Decoder Q14 Q13 Q12 Q11 Q10 Serial

Serial Peripheral Serial Peripheral Serial Peripheral Peripheral 4 different protocols possible First Bit set in NPCS field Serial Serial Peripheral Serial Peripheral Serial Peripheral Serial

Peripheral Peripheral Serial Serial Peripheral Peripheral Q1 Q0 4 different protocols possible 0-3, 4-7, 8-11, 12-14 Peripheral 15 is reserved for no selection 44 RTC : Real Time Clock (1/2) Available on the AT91M55800A only Features

Low power consumption Complete time of day clock Programmable periodic interrupts Alarm Five programmable fields: Month, Date, Sec, Min and Hour Y2K compliant BCD Format 45 RTC : Real Time Clock (2/2) Block Diagram 46 ADC : Analog to Digital Converter (1/2)

Available on the AT91M55800A Features Two identical 4-channel ADC 10-bit resolution Successive Approximation Register (SAR) approach Settable analog input conversion range (dedicated VREF) 11 ADC clock cycles conversion time including 1 ADC clock cycle for sample and hold (e.g. 10s for one channel at maximum clock rate) 4 LSB Maximum Integral Non-linearity Sleep mode (energy saving) Starting modes:

Software trigger External input (A/D trigger) Timers on-chip event signal Dedicated analog power supply pins (VDDA and GNDA) Improve noise rejection End of conversion interrupt 47 ADC : Analog to Digital Converter (2/2) Block Diagram 48 DAC : Digital to Analog Converter (1/2) Available on the AT91M55800A Features

Two identical 1-channel DAC 10-bit resolution 6s maximum settling time Settable analog output range (dedicated VREF) 4 LSB Maximum Integral Non-linearity Starting modes: software trigger Timers on-chip event signal Dedicated analog power supply pins (VDDA and GNDA) Improve noise rejection Data ready interrupt

49 DAC : Digital to Analog Converter (2/2) Block Diagram 50 PIO The Parallel I/O Controller The I/O Pins The PIO lines are controller by two separate and identical PIO controllers called PIOA and PIOB PIO Fast Interrupt PIOA External Interrupt 0 - 3

x25 Peripheral Pins Boot Mode Select (BMS) PIOB x13 General Purpose I/O Lines External Interrupts 4 - 5 x12 Peripheral Pins 52 PIO Control (x12) & Status (8) Registers Peripheral Enable Peripheral Disable Output Enable Output Disable Enable Glitch Filter

Disable Glitch Filter Set Bit Clear Bit 53 PIO Enable Register For PIOB 0 0 0 0 0

0 0 0 0 0 0 0 0 0 0

0 0 0 0 1 1 1 1 1

0 0 0 0 0 0 0 0 54 Parallel I/O Multiplexed with a Bi-directional Signal

55 EBI The External Bus Interface The I/O Pins The EBI generates the signals that control the access to the external memory or peripheral devices. The EBI is fully-programmable and can address up to 128M bytes. A0 A23 (A0 / NLB) D0 D15 EBI NSC0 NSC7 NRD / NOE NWR0 / NWE

MNWR1 / NUB NWAIT 57 Data Bus Width 8-bit Data Bus 16-bit Data Bus 58 2 x 8 bit Data Bus 59 Read Protocol Standard Early

60 Standard Wait States 61 EBI User Interface 62 EBI Chip Select Register EBI_CSR0 EBI_CSR7 ( 0xFFE00000 0xFFE0001C ) 63 Wait States

64 Pages & TDF 65 AIC Advanced Interrupt Controller What are interrupts ? Stops the execution of main software Redirects the program flow, based on an event, to execute a different software subroutine Interrupt behaviour : Main loop : Instruction 1 Instruction 2 Instruction 3

Instruction 4 Instruction 5 Interrupt routine : Instruction A Instruction B Instruction C Return from interrupt 67 Interrupt sources (1) External Interrupts Allows an external event to stop program execution Can alert the core by an edge transition or a level Signal can originate from external peripherals or

systems Example: external switch closure Interrupts AT9 1 68 Interrupt sources (2) Internal Interrupts Originate from on-chip peripherals Timer/Counter Notifies core that peripheral needs servicing Typically can occur at any time

ADC USART Counter overflow End of conversion End of transmission Can originate from software 69 ARM7TDMI Interrupt Sources Two physically independent sources

Fast interrupt : FIQ Used for fast interrupt handling Private registers Enable/disable with F bit in CPSR Last vector in the exception vector table IRQ FIQ ARM7TDMI Processor Interrupt : IRQ Standard interrupt request

Enable/disable with I bit in CPSR 70 Advanced Interrupt Controller (1) Features 8-level Priority Up to 32 Interrupt sources Individually maskable Hardware interrupt vectoring Internal Interrupt sources Level sensitive or edge triggered External Interrupt sources Low/High level sensitive or positive/negative edge triggered 71

Advanced Interrupt Controller (2) Block Diagram 72 Advanced Interrupt Controller (3) Interrupt source 0 1 2 3 4 5 6 7 8 9 10

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

30 31 Interrupt nam e FIQ SW IRQ US0IRQ US1IRQ US2IRQ SPIIRQ TC0IRQ TC1IRQ TC2IRQ TC3IRQ TC4IRQ TC5IRQ W DIRQ PIOAIRQ PIOBIRQ

AD0IRQ AD1IRQ DA0IRQ DA1IRQ RTCIRQ APMCIRQ SLCKIRQ IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0 COMMRX COMMTX Interrupt description Fast interrupt Software interrupt

USART Channel 0 interrupt USART Channel 1 interrupt USART Channel 2 interrupt SPI interrupt Timer Channel 0 interrupt Timer Channel 1 interrupt Timer Channel 2 interrupt Timer Channel 3 interrupt Timer Channel 4 interrupt Timer Channel 5 interrupt W atchdog interrupt Parallel I/O Controller A interrupt Parallel I/O Controller B interrupt Analog to digital Converter Channel 0 interrupt Analog to digital Converter Channel 1 interrupt Digital to Analog Converter Channel 0 interrupt Digital to Analog Converter Channel 1 interrupt Real time clock interrupt Advanced Power Management Controller interrupt

Reserved Reserved Slow Clock interrupt External interrupt 5 External interrupt 4 External interrupt 3 External interrupt 2 External interrupt 1 External interrupt 0 RX Debug Communication Channel interrupt TX Debug Communication Channel interrupt 73 AIC User Interface AT91m55800 Manual page 101 74

Interrupt Vectors Each interrupt source is associated with a Source Vector Register (AIC_SVR0 - AIC_SVR31) which contains the address of the interrupt handler When the Interrupt Vector Register (AIC_IVR) is read, it automatically returns the contents of the source vector register corresponding to the active interrupt ARM Exception vectors AIC Interrupt vectors AIC_ISR ldr pc,[pc,#-&F20] FIQ

0x0000001C IRQ 0x00000018 ABORT (Data) ABORT (Fetch) SWI UNDEF RESET AIC Source vectors 0xFFFFF104 0xFFFFF100 AIC_FVR AIC_IVR AIC_SVR31

0xFFFFF0FC AIC_SVR30 Index = Interrupt Id. AIC_SVR1 AIC_SVR0 0xFFFFF080 75 Interrupt Prioritization (1) The NIRQ line is controlled by an 8-level priority encoder Each source has a programmable priority level of 7 to 0. Level 7 is the highest priority. The AIC manages the prioritization by using an internal stack on which the current interrupt level is automatically

pushed when AIC_IVR is read, and popped when AIC_EOICR (end of interrupt command reg.) is written Between these two events, the software can manage the state and the mode of the core in order to re-enable the IRQ line and to allow an interrupt with a higher priority. 76 Interrupt Prioritization (2) When an interrupt is managed by the processor, R14_irq and SPSR_irq are automatically overwritten without being saved It is mandatory to save these registers before re-enabling the IRQ line and to restore them before exiting the interrupt routine If the interrupt treatment performs function calls (Branch with link), R14_irq is used. In this case, IRQ can not be re-enabled while the processor is in IRQ mode It is mandatory to first change the processor mode to SYSTEM mode in order to keep all exceptions available

77 Interrupt Prioritization (3) The standard sequence of an interrupt handler is: Validate the nested interrupts Save R14_irq and SPSR_irq in the IRQ stack Set the mode bits in CPSR with the SYSTEM Mode value Re-enable IRQ by clearing bit I in CPSR Perfom interrupt treatment call C handler Disable the nested interrupts Disable IRQ by clearing bit I in CPSR Set the mode bits in CPSR with the IRQ Mode value Restore R14_irq and SPSR_irq from the IRQ stack This sequence is automatically preceded by a read of

AIC_IVR and must be followed by a write in AIC_EOICR before exiting from the interrupt 78 Interrupt Prioritization (4/4) 79 Spurious Interrupt (1) A Spurious Interrupt occurs when the ARM7TDMI processor is interrupted and the source of interrupt has disappeared when IVR is read : With any sources programmed to be level sensitive, if the interrupt signal of the AIC input is de-asserted at the same time as it is taken into account by the ARM7TDMI. If an interrupt is asserted at the same time as the software is disabling the corresponding source through AIC_IDCR.

80 Spurious Interrupt (2) The AIC is able to detect these Spurious Interrupts and returns the Spurious Vector when the IVR is read The Spurious Vector can be programmed by the user when the vector table is initialized. It is mandatory for the Spurious Interrupt Service Routine to acknowledge the Spurious behavior by writing to the AIC_EOICR (End of Interrupt) before returning to the interrupted software. Spurious Interrupt Service Routine Sequence:

Adjust and save lr_irq in stack Write the End of Interrupt Command Register Run a trace function if necessary Returns by restoring LR directly in PC 81

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