Instruction Level Parallelism (ILP) - Auburn University

Instruction Level Parallelism (ILP) - Auburn University

Instruction Level Parallelism (ILP) Colin Stevens What is a parallel instruction? ILP is a measure of the number of instructions that can be performed during a single clock cycle. Parallel instructions are a set of instructions that do not depend on each other to be executed. Hierarchy Bit level Parallelism

16 bit add on 8 bit processor Instruction level Parallelism Loop level Parallelism for (i=1; i<=1000; i= i+1) x[i] = x[i] + y[i]; Thread level Parallelism (SMT, multi-core computers) Making Computers Think Parallel Human Write code yourself, directly controlling each processor Compiler

Let the compiler convert your sequential code into parallel instructions. Hardware Implementations of ILP Pipelining Superscalar Architecture Dependency checking on chip. Multiple Processing Elements eg. ALU, Shift VLIW (Very Long Instruction Word

Architecture) Simple hardware, Complex Compiler Multi processor computers Pipelining http://en.wikipedia.org/wiki/Image:Fivestagespipeline.png Superscal ar

http://en.wikipedia.org/wiki/Image:Superscalarpipeline.png Identifying parallel instructions Hardware Techniques Out of order execution Window Size

Speculative execution Branch Prediction Branch Fanout Compiler Techniques Register Renaming ADD $t0,$s1,$2 SW $t0, 0($s3) ADD $t0,s$4,$s5 SW $t0, 0($s6)

Unrolling loops Takes advantage of loop level parallelism References http://en.wikipedia.org/wiki/Image:Fivestagespipeline.png http://en.wikipedia.org/wiki/Image:Superscalarpipeline.png http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/ instrLevParal.html

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