EMU Front-end Electronics T.Y. Ling March 5, 1998

EMU Front-end Electronics T.Y. Ling March 5, 1998

US Cathode FE Board The Ohio State University University of California Davis University of California Los Angeles CERN Cathode FE Board MUX Mature Board - Only Small changes over last 3 Years! 96 Channels CMS CLK Slow control ASIC(chip) Type Preamp-Shaper (16 ch) SCA (16 ch) Comparator (16 ch) ADC (12 bits, 20 MHz) Readout Control FPGA) chip's / CFEB 6 6 6 6 1 7 in

BUCKEYE (ASIC) - amplifies and shapes input pulse SCA (ASIC) - analog storage for 20 MHz sampled input pulse 11.5 in ADC - events with LVL1ACC digitized and sent to DAQ Motherboard (25 nsec/word) Comparator ASIC - generates trigger hit primitives from shaped pulse Controller FPGA - controls SCA storage and digitization L.S. Durkin,ESR 9/00 2 Cathode FE Board Input/Output Signals Inputs Signal LCT L1ACC DAC BUCKEYE Outputs DAQ data Trigger data Monitor Controls

Global-reset Clock FPGA-program JTAG port Downloaded Constants Power 96 channels input from chamber strips from DMB, if CLCT is available, CLCT-->DMB-->CFEB, if CLCT is not available, -->FTC-->DMB-->CFEB, if Calibration mode, DMB-->CFEB From DAQMB, - if CCB is available, CCB-->DMB-->CFEB, or CCB-->FTC-->DMB->CFEB - if CCB is not available, FTC (LCT delay)-->DMB-->CFEB, or, DMB (LCTdelay)-->CFEB, - if Calibration mode, DMB-->CFEB; 0-5V adjustable for external, internal charge injection for BUCKEYE from DAC on DMB +10V and -5V voltage references from DMB Strip charge ADC data, Through 21-bit channel link to DMB Comparator Triads through two 28-bit multiplexers to CLCT; End channel signals to neighboring boards, analog preamp signals and digital comparator signals Temperature sensor output, to DMB, program done from DMB, reset DMB and CFEBs, and synchronize the 50ns clock on DMB and CFEBs 40MHz, from DMB from DMB, re-program the FPGA from PROM on CFEB from DMB, controls: BUCKEYE data shift, FPGA resets, ISP-PROM download, CFEB status monitor, etc. PREBLOCKEND (4 bits) Block Phase Shift PROM programming data (about 500K bits); BUCKEYE working mode (normal, internal capacitor select, external,

kill, 3bits/channel); Comparator timing (3 bits), working mode (2 bits) and threshold +6V: for BUCKEYE clean power (550-600mA) +5V: for SCA, ADC, comparator, etc. (900-1000mA) +3.3V: for FPGA, Channel link, CPLD, etc.(450-500mA) +5V and +3.3V power supplies are subject to change. L.S. Durkin,ESR 9/00 3 BUCKEYE ASIC Physics Demands ~ 150m ME1/2 ~ 300m MEX/X dQ 3% Q Rate is demanding 100 KHz/strip 300 KHz track/chamber 0.8 m AMI CMOS with Linear Capacitor Minuit Fit to Output V(mV) 5 pole semigaussian 1 pole 1 zero tail cancellation 100 nsec peaking time (delta function) 170 nsec peaking time (real pulse)

Gain .9 mV/fC Equivalent Noise 1 mV Nonlinearity < 1 % at 17 MIPS Rate 3 MIPs at 3 MHz with no saturation Two track resolution 125 nsec t(nsec) L.S. Durkin,ESR 9/00 4 BUCKEYE (cont.) (noise) ~ Cx20e/pF +4770e L.S. Durkin,ESR 9/00 5 BUCKEYE / SCA BUCKEYE meets all Requirements ! Switched Capacitor Array (SCA) Block Usage (8 caps/block) SCA Specifications - 96 capacitor for each of 16 channels - LVDS addressing read/write - Simultaneous read/write - Gray Code address sequencing - Input impedance < 300

- Non-Linearity (0-2V) 0.25% - Pedestal Cell-Cell variation 0.25 mV - Maximum Sampling rate 20 MHz - Channel-channel access 100 nsec L.S. Durkin,ESR 9/00 pedestal samples 6 SCA / Controller FPGA SCA meets design specifications ! AMI 0.8m CMOS Controller FPGA (XILINX Virtex) - does SCA bookkeeping - given LCT set aside 2 blocks of 8 capacitors - generates greycode addressing - given LVL1ACC starts digitization - multiplexes ADC output to motherboard - digitization take 25 sec - 12 bit ADC <1 error for 125 Hrs Running L.S. Durkin,ESR 9/00 probability

- controls digitization 300 KHz LCT 3 KHz L1ACC limit BLOCKS 7 Comparator ASIC - 16 channel, 40 MHz output - Input amplified and shaped BUCKEYE output - Generate trigger primitive 1/2 strip hits - Programmable threshold - Programmable timing, working mode = 1.7 mV 0.7m Alcatel J.C. Santiard CERN Efficiency Correct 1/2 strip Nearest N. or Correct L.S. Durkin,ESR 9/00 90.4 % 98.3 % 8

Comparator ASIC ... ASIC Performs to Specifications Highest LHC Rate Removing the Channel Link (3 crossing delay) ... Status - one crossing required to sync signals - prototype has been built and is being tested at Ohio State and UCLA - multiplexer will be rad tested L.S. Durkin,ESR 9/00 9 Calibration BUCKEYE has internal shift register which controls calibration 0 - 5V JTAG Shift Register Modes Normal Precision Ext. Cap (<1%) Int. Cap Small (1x) Int. Cap Medium (2x) Kill 10 pF

stri p 16-ch ASIC 10 pF 16-ch ASIC strip Precision DAQ and Delay on Motherboard Control Pulsing - CCB board generates pseudo pulse, LCT, and LVL1ACC - Precision Ext Cap. Allows gain, linearity, crosstalk, timing measurement. Oscilloscope-like output for each channel. - Any channel can be selectively killed - Trigger logic and thresholds can be checked using small and medium cap L.S. Durkin,ESR 9/00 small + medium cap medium cap small cap 10

Calibration ... Calibration from FNAL Chamber Electronics RMS Pedestal Width (ADC Counts) - 12 bit ADC - 0.5 mV/count 0.54 fC/count - Landau Peak ~ 400 counts - RMS noise for 9216 capacitors Total Noise ~ 1.25 mV ! SCA Capacitor Cell Number - linearity for 480 channels System linearity < 1% at 17 MIPs ! L.S. Durkin,ESR 9/00 11 Calibration ... Gain Constant 1 % RMS - gain varies ~1% within chip - gain varies ~2% chip to chip Chip Pulser + 137Cs (20 kHz/strip)

BUCKEYE can take LHC Rate ! L.S. Durkin,ESR 9/00 12 Timing / Slow Control Timing and Synchonization Cathode FE Board allow 1 Beam Crossing uncertainty on LCT relative to LVL1ACC Timing is a Trigger Issue - FE Board 40 MHz clock has programmable delay on Motherboard - Comparitor 40 MHz clock has programmable delay on CLCT Board - LCT and LVL1ACC synchronized to 40 MHz Clock Interface with Fast and Slow Control Fast Control Signals (CCB) to FE Board - reprogram logic (see rad discussion) - reset logic - pulse, pseudo-LCT, pseudo-LVL1ACC (calibration) Slow Control Signals to FE Board - JTAG signals, TDO,TDI, TCLK, TMS L.S. Durkin,ESR 9/00 13 Slow Control Slow Control System one PC (running SCADA CMS slow control software) serves 24 crates

ethernet 10 Base-T embedded VME computer VME Bus within Crate DAQ Motherboard has VME interface -FPGA VME interface generates JTAG for FE Board Embedded VME Computer: Prototype system achieved 3 Mbit/s loading Spartan FPGA Cathode FE Board Slow Control Buckeye Shift Registers 1 Xilinx EPROM (program and readback) 1 Xilinx Virtex (readback) FPGA status checks (check on startup) comparator thresholds comparator mode/timing thermistor (temperature) access boards unique serial number L.S. Durkin,ESR 9/00 14 Monitoring Each FE Board has a 4 bit Beam Crossing counter - stored in data transferred to Motherboard Each Digitized event has 8 checksum words (CRC15) - stored in data transferred to Motherboard - sensitive to channel link problems LCT-LVL1ACC Coincidence Calculated both on FE Board and Motherboard Separately

- motherboard knows when FE data not present - lack of data reported to DAQ FE Boards send fixed data length records to FIFO on Motherboard - motherboard knows when data is missing - lack of data reported to DAQ - CFEB-Motherboard transmission timeout (10 sec) Most failures will be detected before Periodic Radiation reload and resets allowing CCB to Reset the system ! L.S. Durkin,ESR 9/00 15 Radiation Tests Radiation Levels in Endcap Muon Calculations by M. Huhtinen E>100 KeV 1012 1011 ME11 ME12 ME13 1010 Neutron Flux (cm-2s-1)

Neutron Fluence (cm-2) Integrated over 10 LHC years (5x107 s at 1034 cm-2s-1) Neutron Fluence (>100 keV): (0.02 - 6) x 1011 cm-2 Total Ionizing Dose: (0.007 - 1.8) kRad ME11 10-6 Radius (cm) L.S. Durkin,ESR 9/00 10-3 1 103 Neutron Energy (MeV) 16 Radiation Tests ... Worst-case Radiation Environment (Use calculated levels times a safety factor of 3) Measure SEE (SEU and SEL) cross sections for neutron fluence of 2x1012 cm-2 Measure TID effects up to a dose of 5 kRad Measure degradation for an equivalent neutron fluence of 2x1012 cm-2 63 MeV

Protons 1 MeV Neutrons (UC Davis) (Ohio State) SEU, SEL, TID Bipolar Devices SEU, SEL, TID Displacement ~12 min exposure Gain vs Dose 3000 Expected dose in 10 LHC 2000 years 1000 0 new runs w/ same chip Curves for all

16 channels 100 200 Dose (Krad) L.S. Durkin,ESR 9/00 8 RMS Noise (mV) Output Amplitude (ADC counts) CMOS Devices Noise vs Dose 6 4 2 300 0 0 10

20 Dose (Krad) 17 30 Radiation Test Summary Device (Function) XILINX Spartan XCS30XL (Readout Controller) XILINX Spartan XCS30XL (Multiplexer) XILINX CPLD XC9536XL (Chip 1) XILINX CPLD XC9536XL (Chip 2) XILINX Virtex XCV50 (Readout Controller & MUX) Channel Link Receiver Channel Link Transmitter Proton Fluence Dosage Number of SEU Xection (1011 cm-2) (kRad) SEU's (10-10 cm2) 1.0 13.4 27

2.7 2.9 38.1 34 1.2 2.8 42.7 106 3.1 41.3 117 0.9 14.8 14.8 12.5 200 200 16 277 1023

3.8 1.7 1.9 6.9 Fluence = 2.8 x 1012 / cm2 Following devices passed the test LM1117-adj (adjustable voltage regulator) LM4120-2.5 (voltage reference; 3.3 V, 5 mA) LM4120-1.8 (voltage reference; 3.3 V, 5 mA) LM4041 (shunt voltage reference) SDA321 (Diode Array reversed biased) Red LED AD8011 (300 MHz Current Feedback OpAmp) Need a rad-tolerant 2.5 V regulator Good candidate identified. Presently testing. L.S. Durkin,ESR 9/00 18 Radiation Tests ... Cumulative effects Total ionization dosage (with 63 MeV protons) No deterioration of analog performance up to 10 krad

for all three CMOS ASICs All FPGAs survive beyond dosage of 30 krad Displacement damage (with 2x1012 cm-2 ns @ 1 MeV) Usable voltage regulators and references identified Protection diodes OK Single-Event Effects No latch-up for all ASICs up to 2x1012 p cm-2 Single Event Upset (SEU) Cross sections measured for all FPGAs, C-Links. All SEUs in FPGAs recoverable by reloading SEU Rate on FE Board given by Controller FPGA Controller FPGA (XILINX Virtex) - triple voting logic on crucial gates - SEU cross section 1.7x10-10cm-2 (410,000 s/SEU) Must Reload Virtex Every ~17 minutes L.S. Durkin,ESR 9/00 19 FPGA Reload Scheme EPROM (XC1802) JTAG Reloadable - 2.76x1011p/cm2 37.0 kRad - 3 SEUs, No Memory Errors - Must reload every 1.5 LHC years ! CCB Program FPGA Reset FPGA JTAG Program EPROM Readback EPROM

EPROM 5 msec load Virtex JTAG Readback FPGA Schematic FE Board Loading Reload every 17 minutes or when error is detected Note: Almost all virtex errors will be detected as errors by DAQ system! L.S. Durkin,ESR 9/00 20 Magnetic Field Test FE Board in 3 Tesla Field MRI Facility Ohio State U. Hospital 8 Tesla Field Research Magnet Tested calibration, noise, pedestal, linearity. Only difference was a time shift of 6 nsec Passive Delays - Rhombus LVMDM 100 nsec contain iron have switched to Passive Delays

- Data Delay Devices 3D7105 for short delays - Virtex Delay-Lock loops for long delays t (nsec) 6 nsec delay no difference seen L.S. Durkin,ESR 9/00 21 Spark Protection HV 4.2 KV Spark Gap 100 M 70nH Buckeye 1nF 100pF 15 anode protection

chamber protection circuit Scheme has protected Buckeye for Simulated 3000 Sparks Two Options Under Study 1. Inductor is Chamber- FE Board cable (100 nH/ft) 2. Put 96 Air-core (~68 nH) Inductors on FE Board L.S. Durkin,ESR 9/00 22 Burn-In We have procured a large oven at OSU What do other people do ? CDF: 50-60 C for 8-24 Hrs US Military: 125 C for 320 Hrs CDF sufficient for things like backward tantalums no sensitivity to semiconductor failure Replacing boards in CMS forward muon chambers will be difficult We will start conservatively and measure failure rate vs time. Hopefully full US military burn-in will not be needed ! L.S. Durkin,ESR 9/00

23 Production PC boards will be etched and stuffed commercially ASIC Testing BUCKEYE Preamp/Shaper ~ 15000 ASIC chips will be produced by AMI Bonded in Indonesia by AIT LTD Tested at Ohio State Measure gain, noise, linearity peaking time, delay time, for each channel 1000 chips Yield ~50% channels AMI Preproduction Width 1.6 % (problem found in one of two AMI assembly lines. They are fixing and will make new samples. Yield increase to >80%) Gain (ADC Channels) L.S. Durkin,ESR 9/00 24

Production SCA ASIC AMI will manufacture wafers AMI will measure chips guaranteeing quality AMI will bond chips Comparator ASIC Alcatel will manufacture wafers an outside company will measure chips Chips will be bonded in Hong Kong Alcatel Preproduction yield 66 % (working on it) chips are excellent L.S. Durkin,ESR 9/00 25 Production ... Stuffed Boards will be tested and debugged before Burn-In and after Burn-In at O.S.U. Boards will be measured and debugged on computerized tester presently being designed and built at O.S.U. Data Cables - Cables are being assembled and tested by outside companies 9 m skew-clear cable tester

L.S. Durkin,ESR 9/00 26 Material Safety FE Board Cables Cable FE Board - FE Board Chamber - FE Board FE Board - Motherboard FE Board - CLCT Conductors 40 34 25 pair 25 pair Insulation Shield Jacket Manufacturer HF Polyolefin none none 3M HF FR Polyolefin HF FR Polyolefin HF FR Polyolefin Amphenol HF FR Polyolefin HF FR Polyolefin HF FR Polyolefin Amphenol HF FR Polyolefin HF FR Polyolefin HF FR Polyolefin Amphenol (all board and cable connectors have glass filled

Polyester (PBT) rated UL 94-V0 as the insulator) Following CMS Cable Colour Codes: FE Board - Motherboard Cable will be BLUE Date: Thu, 11 May 2000 08:58:49 +0200 From: Marc TAVLET Subject: Re: cable approval To: [email protected] Cc: [email protected], [email protected], [email protected], [email protected] Dear Mr Ling, Yes, I have received the information on the Amphenol/Spectra-Strip cable (Round, jacketed, 25 shielded parallel pairs, 28 AWG). The construction of the cable seems to be very good as regard to fireresistance; the cable is rated IEC-332-3 which is ok. The proposed materials are halogen-free. Also the PBT used for the connectors is rated UL 94-V0. In conclusion, this cable and connector are perfectly acceptable from a fire-safety point of view. I approve their use. Thanks for your collaboration. Marc Tavlet L.S. Durkin,ESR 9/00 27 Maintenance Ohio State University will maintain the FE Boards 10 % Spare Boards will be Built We anticipate swapping bad boards during accesses and fixing them. Each board has a unique electronic serial number. Swaps can be monitored using software.

Click to edit Master title Conclusion style Cathode FE Board Meets All Design Specifiations! It is time to start procuring parts and begin manufacturing... L.S. Durkin,ESR 9/00 28

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