Semiconductor Device Modeling and Characterization EE5342 Lecture 35 Spring 2011 Professor Ronald L. Carter [email protected] http://www.uta.edu/ronc/ Flat-band parameters for p-channel (n-subst) n substrate : VFB Q'ss ms (nochange) C'Ox Ox

C'Ox , Q'ss is the Ox/Si chg den xOx For a p poly- Si gate, s m s NvNd Eg Nd 0 ms Vt ln 2 Vt ln ni ni 2q rlc L3529Apr2011 Eg q Fully biased pchannel VT calc n substrate : VG, at threshold VT

VT VC VFB 2n Q'd,max C'Ox VFB V Nd 0, Q'd,max qNdxd,max, n Vt ln ni 2 2 n VC VB xd,max , V 0 qNd rlc L3529Apr2011

p-channel VT for VC = VB = 0 Fig 10.21* rlc L3529Apr2011 Ion implantation rlc L3529Apr2011 Dotted box approx rlc L3529Apr2011 Nimpl dx NaiXi

0 areaunder dashedcurve ' Qss areaunderdotted curve ' Qss , before impl qNaiX i di X i Xd, max Na

Nd , F NaiX To get Vt as desired,implantNai Xi qNaiXi to get Vt 2.43, etc ' Cox rlc L3529Apr2011 di Mobilities rlc L3529Apr2011 Differential charges for low and high freq

high freq. From Fig 10.27* rlc L3529Apr2011 Ideal low-freq C-V relationship Fig 10.25* rlc L3529Apr2011 Comparison of low and high freq C-V Fig 10.28* rlc L3529Apr2011

Effect of Qss on the C-V relationship Fig 10.29* rlc L3529Apr2011 n-channel enhancement MOSFET in ohmic region Channe l 0< VT< VG VS = 0 0< VD< VDS,sat n+

Depl Reg rlc L3529Apr2011 EOx,x> 0 e-e- e- e- e- p-substrate VB < 0 n+ Acceptor s Conductance of

inverted channel Qn = - COx(VGC-VT) ns = COx(VGC-VT)/q, (# inv elect/cm2) The conductivity n = (ns/t) q n G = n(Wt/L) = ns q n (W/L) = 1/R, VD soL I dL C ' V

V V WdV n Ox G C T I = V/R = dV/dR, dR = dL/(nsqnW) 0 rlc L3529Apr2011

VS Basic I-V relation for MOS channel W nCOx 2 ID 2 VG VT VDS VDS , VDS VG VT 2L At VDS VDS,sat VG VT , Q'n y L 0 Sat. so let I D be given by I D VDS,sat , for VDS VDS,sat VG VT so

I D I D,sat rlc L3529Apr2011 W nCOx VG VT 2 2L I-V relation for n-MOS (ohmic reg) C' W n Ox ID 2

2 2 VG VT VDS VDS . Note for L VDS VG VT VDS,sat, result is non- physical. At VDS,sat, n's,yL 0 ID ID,sat ohmi c nonphysical

assumethat channelcurr. is const for VDS VDS,sat I D,sat nC'Ox W VGS VT 2 2 L rlc L3529Apr2011 saturate d VDS VDS,sat

Universal drain characteristic nC'Ox W I D1 1V 2 2 L nC'Ox W 2 I D,sat VDS 2 L ID VGS=VT+3V

9ID1 ohmic 4ID1 saturated, VDS>VGS-VT VGS=VT+2V VGS=VT+1V ID1 rlc L3529Apr2011 VDS Characterizing the n-ch MOSFET VD

ID ID D G S slope B nC'Ox W L 2

VDS VGS , VT 0 VDS VGS VT , so nC'Ox W VGS VT 2 I D,sat 2 L rlc L3529Apr2011 VT VGS Low field ohmic characteristics C' W ID

n Ox 2 2 VGS VT VDS VDS , L 2 for ohmic region. Furthermore, let VDS VG VT , so that W I D nC'Ox VGS VT VDS L W KP VGS VT VDS , KP nC'Ox

L dI D W KP VDS dV L GS V V V DS rlc L3529Apr2011 G T MOSFET Device Structre Fig. 4-1, M&A*

rlc L3529Apr2011 4-7a rlc L3529Apr2011 (A&M) Figure 4-7b (A&M) rlc L3529Apr2011 Figure 4-8a rlc L3529Apr2011 (A&M)

Figure 4-8b rlc L3529Apr2011 (A&M) Body effect data Fig 9.9** rlc L3529Apr2011 MOSFET equivalent circuit elements Fig 10.51* 2 1

Cgs COx , Cgd COx , COx WLC'Ox 3 3 rlc L3529Apr2011 n-channel enh. circuit model G RG S RB Cgs RDS Cgd

Cbs Idrain DSS DSD Cbd RD D RB rlc L3529Apr2011 B Cgb MOS small-signal equivalent circuit

Fig 10.52* rlc L3529Apr2011 MOSFET circuit parameters Transconduc tance I D gm VGS VDS W nC'Ox VGS VT , saturation gms

L W nC'Ox gmL VDS , ohmicregion L rlc L3529Apr2011 MOSFET circuit parameters (cont) Output or drain conductanc e I D gd VDS V GS gds 0, saturation

gdL rlc L3529Apr2011 W nC'Ox VGS VT VDS , ohmic L Substrate bias effect on VT (body-effect) Letting VT calculation be relative to Source VT VS VFB 2 p xd,max VT VSB rlc L3529Apr2011

qNaxd,max 2 2 p VSB C'Ox qNa 2 Si qNa 0 C'Ox , where

, so VT VT VSB 2 p VSB 2 p Body effect data Fig 9.9** rlc L3529Apr2011 Fully biased nchannel VT calc p substrate: VG, at threshold VT

VT Vs VFB 2p Q'd,max VFB V C'Ox ni p Vt ln 0, Q'd,max qNaxd,max, Na xd,max rlc L3529Apr2011 2 2 p VB Vs

qNa , V 0 Values for ms with silicon gate NCNa n poly to p - Si : ms Si Si Vt ln 2 ni NCNa Eg Na Note : Vt ln 2 Vt ln

ni ni 2q Eg NC p poly to n - Si : ms Si Si Vt ln q Nd NC Eg Nd Note : Vt ln Vt ln Nd 2q ni rlc L3529Apr2011 rlc L3529Apr2011

Fig 8.11** |Qd,max|/q (cm-2) xd,max (microns) Qd,max and xd,max for biased MOS capacitor I-V relation for n-MOS C' W n Ox ID 2

2 2 VG VT VDS VDS . Note for L VDS VG VT VDS,sat, result is non- physical. At VDS,sat, n's,yL 0 ID ID,sat ohmi c nonphysical

assumethat channelcurr. is const for VDS VDS,sat I D,sat nC'Ox W VGS VT 2 2 L rlc L3529Apr2011 saturate d VDS VDS,sat MOS channellength modulation

Fig 11.5* rlc L3529Apr2011 Analysis of channel length modulation Assume the DR change the channel L length modulation , so I'D ID L L 2Si L 2 p VDS,sat VDS qNa

2 p VDS,sat , VDS VDS VDS,sat I D,sat rlc L3529Apr2011 nC' Ox W VGS VT 2 1 VDS 2 L References CARM = Circuit Analysis Reference Manual, MicroSim Corporation, Irvine, CA, 1995.

M&A = Semiconductor Device Modeling with SPICE, 2nd ed., by Paolo Antognetti and Giuseppe Massobrio, McGraw-Hill, New York, 1993. **M&K = Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986. *Semiconductor Physics and Devices, by Donald A. Neamen, Irwin, Chicago, 1997 rlc L3529Apr2011