Design Productivity Crisis - 國立臺灣大學

Design Productivity Crisis - 國立臺灣大學

GTX: The GSRC Technology Extrapolation System, A Living Roadmap A. Caldwell, A. B. Kahng, F. Koushanfar, H. Lu, I. Markov, M. Oliver and D. Stroobandt DARPA Overview Introduction Previous roadmapping efforts Overview of GTX: goal and structure Fundamental features Demonstration Example use scenarios: Roadmap emulation, development, and maintenance Roadmap evaluation and comparison 11/

2 Introduction: Technology Extrapolation Evaluates impact of What is the most power-efficient noise management strategy? design technology process technology How and when do L, SOI, SER, etc. matter? Evaluates impact on achievable design associated design problems

Questions to be addressed Will layout tools need to perform process simulation to efficiently model cross-die and cross-wafer manufacturing variation? Sets new requirements for CAD tools and methodologies Roadmaps: familiar and influential example 11/ 3 Introduction: Roadmapping Roadmapping efforts drive development of design technology: System architects, designers, CAD managers use roadmaps to determine

tough problems risks, EDA suppliers use roadmaps to determine R&D investment product pipeline Government and consortia use roadmaps to determine levels of investment Roadmaps serve as a guide to the most promising directions, the most critical problems 11/ 4

Roadmap Process and Its Implications Basic Technological Assumptions Basic Methodological Assumptions Models and Discussion Implications to the Community Translation to Specific Research Agendas Research Proposed to Implement Agenda 11/ Timing closure is a hard problem

and will only get harder We will fund research on timing-aware partitioning R. Newton, ICCAD99 panel 5 Roadmap Process Basic Technological Assumptions Basic Methodological Assumptions Models and Discussion New models

Implications to the Community Timing closure is a hard problem and will only get harder Heres how my work is critical for addressing your problem Couched in Terms of Roadmap Implications Research Proposed to Solve Hard Problem 11/ I can make a breakthrough in technology or methodology R. Newton, ICCAD99 panel

6 Introduction: Roadmapping Difficulties of roadmapping No crystal ball New technologies, new circuit techniques, new design methodologies and tools Always difficult to predict achievable design, especially in the future Roadmaps rely on Models: technology projections, design attributes, design tools Calibrations: measurements of technology and design parameters 11/

7 Roadmapping in the past Previous and ongoing efforts ITRS Roadmaps Tools: SUSPENS, GENESYS, RIPE, BACPAC, Numerous tools in industry Observations Predict same parameters but with different assumptions, inputs Lack of documentation and visibility into internal calculations Single inference chain for a given output (hard-coded modeling) Inflexible: user cannot define studies of other, related parameters Near-total duplication of effort Missing: models of CAD tools and optimizations (what is really achievable?) Missing: scope, comprehensive coverage 11/

8 Questions To Ask About Roadmaps How do different roadmap predictions compare? How to evaluate underlying models? (sanity checks) How do we reuse and extend models to encompass new aspects of technology, new axes of achievable design? What is the impact of modeling choices on predictions? Need a new infrastructure, new concept! 11/ 9 Previous Systems versus Ideal System Same parameters but

Flexibility different assumptions Inflexible, not easy to Quality add other studies Hard-coded, no easy changes No internal visibility Duplication of effort 11/ Transparency Prevention of redundant effort

10 Goals of A New Technology Extrapolation System Flexibility Interactively edit chains of relations between parameters Define new parameters and relations between them Perform specific studies (but different studies at different times) Quality Continuous improvements World-wide participation of experts Transparency Prevention of redundant effort 11/ 11 Goals of New Technology Extrapolation (cont.)

Flexibility Quality Transparency Open-source mechanism Models are visible to the user Prevention of redundant effort Permanent repository of first choice Adoptability and maintainability 11/ 12 GTX: GSRC Technology Extrapolation System GTX is set up as a framework for technology extrapolation Data Knowledge

Models Derivation Implementation Presentation Flexibility, quality, visibility allow a living roadmap: emulate existing roadmap (modeling) efforts develop new roadmaps (models) evaluate roadmaps (models) compare roadmaps (models) to each other 11/ 13 GTX Structure Knowledge representation: Parameters (description of technology, circuit and design attributes) Rules (methods to derive unknown parameters from known ones):

closed-form models executable algorithm implementations table-lookups Rule chains (serialized user-defined rules) interactive specification and comparison of alternative modeling choices Implementation Execution by a derivation engine to perform studies Embedding into GUI for ease of use, interactivity, display of results See poster for details of GTX framework 11/

14 Knowledge Representation Rules and parameters are specified separately from the derivation engine Human-readable ASCII grammar #parameter dl_chip #type double #units {m} #default 1e-2 #description chip side length #reference #endparameter 11/

#rule BACPAC_dl_chip #description #output double {m} dl_chip; #inputs double {m^2} dA_chip; #body sqrt(dA_chip) #reference #endrule 15 Knowledge Representation (cont.) Rules and parameters are specified separately from the derivation engine Human-readable ASCII grammar Benefits: Easy creation and sharing of parameters / rules by multiple users

D. Sylvester and K. Cao: device and power modules that drop in to GTX Extensible to models of arbitrary complexity (specialized prediction methods, technology data sets, optimization engines) Avant! Apollo or Cadence SE P&R tool: just another wirelength estimator Applies to any domain of work in semiconductors, VLSI CAD 11/ Transistor sizing, single wire optimizations, system-level wiring predictions, 16

Parameter and Rule Naming Importance of consistent naming cannot be overstated Naming conventions for parameters [] _ _ {[qualifier] _ } _ {} _ [] _ [] _ [] Example: r_int_tot_lyr_pu_dl Benefits: Relatively easy to understand parameter from its name Distinguishable (no two parameters should have the same name) r_int (interconnect resistance) = r_int (interconnect resistivity) ? Unique (no two names for the same parameter) R_int = R_wire ? Sortable (important literals come first) 11/ 17

Additional Features Optimization over a collection of rules (with constraints) Example: buffer insertion for minimal delay with area constraints Executables can be called Example: various optimizations of global delay through IPEM (Interconnect Performance Estimation Models, J. Cong, UCLA) Internal code rules for optimizations Example: optimization of number and size of repeaters for global wires Storing of calibration data (e.g., technology files) for known process, design points 11/ 18

Additional Features (cont.) Visualization (plotting, printing, saving to file) Sweeping over sets of input values Example: clock frequency for different Rent exponents and varying logic depth 11/ 19 GTX: Open and User-friendly Openness in grammar, parameters and rules Easy sharing of data in research environment Contributions from other groups Allows developing of proprietary models Separation between supplied (shared) and user-defined

parameters / rules GTX offers usability behind firewalls Framework for sharing results instead of data is planned Multi-platform (SUN Solaris, Windows, Linux) 11/ 20 Demonstration 11/ 21 GTX Current Status Emulation of Cycle-time models of SUSPENS (with extension by Takahashi),

BACPAC, Fisher (ITRS) Interconnect tuning studies Main modules Clock / power SOI Domino logic Device and Power Global interconnect System-level power Packaging Reliability and Yield 11/ 22 GTX Current Status Evaluation of cycle-time models

Parameter sensitivity Comparison between cycle-time models Model sensitivity Development of new models Model of via impact on required routing resources (number of layers, pitch, etc.) 11/ 23 Evaluation: Parameter Sensitivity Change parameter values and observe resulting difference in outputs

See poster on Sensitivity Analysis for further details 11/ 24 Comparison: Model Sensitivity Replace rule in a models rule chain by another models rule and observe the difference in outputs BACPAC BACPAC with rule from Fisher See poster on Sensitivity Analysis for further details 11/ 25 Development: Via Impact Model

Goal: model impact of vias on layer track utilization Only taking into account area taken by via is not enough Stochastic model of the number of wires blocked by vias used to estimate the via impact Via impact model improves prediction of number of layers needed for the routing Verified with recent 4LM block, Cadence Silicon Ensemble P&R See poster on Via Impact Model for further details 11/ 26 Conclusion GTX: a new framework for roadmapping models and technology

extrapolation efforts Flexible and extensible Enables easy reuse of models Provides a common parameter base between all models Provides user interaction Relies on open-source and contributions by expert users Living Roadmap Technology extrapolation becomes easier More principled understanding of requirements for CAD tools 11/ 27 GTX Project Information Design: A. Caldwell, A. B. Kahng, I. Markov, M. Oliver Implementation: M. Oliver Knowledge gathering and implementation: A. B. Kahng,

F. Koushanfar, H. Lu, D. Stroobandt Detailed information and downloading of prototype version of GTX: To contact the developers, ask questions, send comments, or to contribute with models to be included in GTX, please send E-mail to [email protected] 11/ 28 Acknowledgements MARCO GSRC F.W.O. (Belgium) for D. Stroobandts grant to visit UCLA Dr. Phil Fisher, Dr. Dennis Sylvester and Kevin Cao for providing access to their models and helpful inputs

Professors Ken Rose, James Meindl, Scott Wills and Kurt Keutzer for fruitful discussions 11/ 29

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