Chapter 2

Chapter 2

Chapter 4 MARIE: An Introduction to a Simple Computer Chapter 4 Objectives Learn the components common to every modern computer system. Be able to explain how each component contributes to program execution. Understand a simple architecture invented to illuminate these basic concepts, and how it relates to some real architectures.

Know how the program assembly process works. 2 4.2 CPU Basics The computers CPU fetches, decodes, and executes program instructions. The two principal parts of the CPU are the datapath and the control unit. The datapath consists of an arithmetic-logic unit and storage units (registers) that are interconnected by a data bus that is also connected to main memory. Various CPU components perform sequenced operations

according to signals provided by its control unit. 3 4 Computer System 5 4.2 CPU Basics Registers hold data that can be readily accessed by

the CPU. They can be implemented using D flip-flops. A 32-bit register requires 32 D flip-flops. The arithmetic-logic unit (ALU) carries out logical and arithmetic operations as directed by the control unit. The control unit determines which actions to carry out according to the values in a program counter register and a status register. 6

4.3 The Bus The CPU shares data with other system components by way of a data bus. A bus is a set of wires that simultaneously convey a single bit along each line. Two types of buses are commonly found in computer systems: point-to-point, and multipoint buses. These are point-topoint buses: 7

4.3 The Bus Buses consist of data lines, control lines, and address lines. While the data lines convey bits from one device to another, control lines determine the direction of data flow, and when each device can access the bus. Address lines determine the location of the source or destination of the data. The next slide shows a model bus configuration. 8

Buses 9 4.3 The Bus A multipoint bus is shown below. Because a multipoint bus is a shared resource, access to it is controlled through protocols, which are built into the hardware. 10

4.3 The Bus In a master-slave configuration, where more than one device can be the bus master, concurrent bus master requests must be arbitrated. Four categories of bus arbitration are: Daisy chain: Permissions Distributed using self-detection: are passed from the highestDevices decide which gets the bus priority device to the among themselves. lowest. Distributed using collision Centralized parallel: Each detection: Any device can try to

device is directly connected use the bus. If its data collides to an arbitration circuit. with the data of another device, it tries again. More on Buses 11 4.4 Clocks Every computer contains at least one clock that synchronizes the activities of its components.

A fixed number of clock cycles are required to carry out each data movement or computational operation. The clock frequency, measured in megahertz or gigahertz, determines the speed with which all operations are carried out. Clock cycle time is the reciprocal of clock frequency. An 800 MHz clock has a cycle time of 1.25 ns. 12 4.4 Clocks Clock speed should not be confused with CPU

performance. The CPU time required to run a program is given by the general performance equation: We see that we can improve CPU throughput when we reduce the number of instructions in a program, reduce the number of cycles per instruction, or reduce the number of nanoseconds per clock cycle. We will return to this important equation in later chapters. 13 4.5 The Input/Output Subsystem

A computer communicates with the outside world through its input/output (I/O) subsystem. I/O devices connect to the CPU through various interfaces. I/O can be memory-mapped-- where the I/O device behaves like main memory from the CPUs point of view. Or I/O can be instruction-based, where the CPU has a specialized I/O instruction set. We study I/O in detail in chapter 7. 14

4.7 Interrupts The normal execution of a program is altered when an event of higher-priority occurs. The CPU is alerted to such an event through an interrupt. Interrupts can be triggered by I/O requests, arithmetic errors (such as division by zero), or when an invalid instruction is encountered. Each interrupt is associated with a procedure that directs the actions of the CPU when an interrupt occurs. Nonmaskable interrupts are high-priority interrupts that cannot be ignored.

15 4.8 MARIE We can now bring together many of the ideas that we have discussed to this point using a very simple model computer. Our model computer, the Machine Architecture that is Really Intuitive and Easy, MARIE, was designed for the singular purpose of illustrating basic computer system concepts. While this system is too simple to do anything useful

in the real world, a deep understanding of its functions will enable you to comprehend system architectures that are much more complex. 16 4.8 MARIE This is the MARIE architecture shown graphically. 17 4.8 MARIE The MARIE architecture has the following

characteristics: Binary, two's complement data representation. Stored program, fixed word length data and instructions. 4K words of word-addressable main memory. 16-bit data words. 16-bit instructions, 4 for the opcode and 12 for the address. A 16-bit arithmetic logic unit (ALU). Seven registers for control and data movement. 18

4.8 MARIE MARIEs seven registers are: Accumulator, AC, a 16-bit register that holds a conditional operator (e.g., "less than") or one operand of a two-operand instruction. Memory address register, MAR, a 12-bit register that holds the memory address of an instruction or the operand of an instruction. Memory buffer register, MBR, a 16-bit register that holds the data after its retrieval from, or before its placement in memory.

19 4.8 MARIE MARIEs seven registers are: Program counter, PC, a 12-bit register that holds the address of the next program instruction to be executed. Instruction register, IR, which holds an instruction immediately preceding its execution. Input register, InREG, an 8-bit register that holds data read from an input device.

Output register, OutREG, an 8-bit register, that holds data that is ready for the output device. 20 4.8 MARIE This is the MARIE architecture shown graphically. 21 4.8 MARIE The registers are interconnected, and connected with

main memory through a common data bus. Each device on the bus is identified by a unique number that is set on the control lines whenever that device is required to carry out an operation. Separate connections are also provided between the accumulator and the memory buffer register, and the ALU and the accumulator and memory buffer register. This permits data transfer between these devices without use of the main data bus. 22

4.8 MARIE This is the MARIE data path shown graphically. 23 4.8 MARIE A computers instruction set architecture (ISA) specifies the format of its instructions and the primitive operations that the machine can perform. The ISA is an interface between a computers

hardware and its software. Some ISAs include hundreds of different instructions for processing data and controlling program execution. The MARIE ISA consists of only thirteen instructions. 24 4.8 MARIE This is the format of a MARIE instruction: The fundamental MARIE instructions are:

25 4.8 MARIE This is a bit pattern for a LOAD instruction as it would appear in the IR: We see that the opcode is 1 and the address from which to load the data is 3. 26

4.8 MARIE This is a bit pattern for a SKIPCOND instruction as it would appear in the IR: We see that the opcode is 8 and bits 11 and 10 are 10, meaning that the next instruction will be skipped if the value in the AC is greater than zero. What is the hexadecimal representation of this instruction? 27 4.8 MARIE Each of our instructions actually consists of a

sequence of smaller instructions called microoperations. The exact sequence of microoperations that are carried out by an instruction can be specified using register transfer language (RTL). In the MARIE RTL, we use the notation M[X] to indicate the actual data value stored in memory location X, and to indicate the transfer of bytes to a register or memory location. 28

4.8 MARIE The RTL for the LOAD instruction is: MAR X MBR M[MAR] AC MBR Similarly, the RTL for the ADD instruction is: MAR X MBR M[MAR] AC AC + MBR 29

4.8 MARIE Recall that SKIPCOND skips the next instruction according to the value of the AC. The RTL for the this instruction is the most complex in our instruction set: If IR[11 - 10] = 00 If AC < 0 then else If IR[11 - 10] If AC = 0 then else If IR[11 - 10] If AC > 0 then

30 then PC = 01 PC = 11 PC PC + 1 then

PC + 1 then PC + 1 4.9 Instruction Processing The fetch-decode-execute cycle is the series of steps that a computer carries out when it runs a program. We first have to fetch an instruction from memory, and place it into the IR. Once in the IR, it is decoded to determine what needs to be done next. If a memory value (operand) is involved in the

operation, it is retrieved and placed into the MBR. With everything in place, the instruction is executed. The next slide shows a flowchart of this process. 31 4.9 Instruction Processing 32 4.9 Instruction Processing All computers provide a way of interrupting the fetch-decode-execute cycle.

Interrupts occur when: A user break (e.,g., Control+C) is issued I/O is requested by the user or a program A critical error occurs Interrupts can be caused by hardware or software. Software interrupts are also called traps. 33 4.9 Instruction Processing

Interrupt processing involves adding another step to the fetch-decode-execute cycle as shown below. The next slide shows a flowchart of Process the interrupt. 34 4.10 A Simple Program Consider the simple MARIE program given below. We show a set of mnemonic instructions stored at addresses 100 - 106 (hex): 35

4.10 A Simple Program Lets look at what happens inside the computer when our program runs. This is the LOAD 104 instruction: 36 4.10 A Simple Program Our second instruction is ADD 105: 37

4.13 A Discussion on Decoding A computers control unit keeps things synchronized, making sure that bits flow to the correct components as the components are needed. There are two general ways in which a control unit can be implemented: hardwired control and microprogrammed control. With microprogrammed control, a small program is placed into read-only memory in the microcontroller. Hardwired controllers implement this program using digital logic components.

38 4.13 A Discussion on Decoding Your text provides a complete list of the register transfer language for each of MARIEs instructions. The microoperations given by each RTL define the operation of MARIEs control unit. Each microoperation consists of a distinctive signal pattern that is interpreted by the control unit and results in the execution of an instruction. Recall, the RTL for the Add instruction is:

MAR X MBR M[MAR] AC AC + MBR 39 4.13 A Discussion on Decoding Each of MARIEs registers and main memory have a unique address along the datapath. The addresses take the

form of signals issued by the control unit. How many signal lines does MARIEs control unit need? 40 4.13 A Discussion on Decoding Let us define two sets of three signals. One set, P2, P1, P0, controls reading from

memory or a register, and the other set consisting of P5, P4, P3, controls writing to memory or a register. The next slide shows a close up view of MARIEs MBR. 41 4.13 A Discussion on Decoding This register is enabled for reading when P0 and P1 are high, and it is enabled for writing when P3 and P4 are high

42 4.13 A Discussion on Decoding Careful inspection of MARIEs RTL reveals that the ALU has only three operations: add, subtract, and clear. We will also define a fourth do nothing state. The entire set of MARIEs control signals consists of: Register controls: P0 through P5.

ALU controls: A0 through A3 Timing: T0 through T7 and counter reset Cr 43 4.13 A Discussion on Decoding Consider MARIEs Add instruction. Its RTL is: MAR X MBR M[MAR] AC AC + MBR

After an Add instruction is fetched, the address, X, is in the rightmost 12 bits of the IR, which has a datapath address of 7. X is copied to the MAR, which has a datapath address of 1. Thus we need to raise signals P2, P1, and P0 to read from the IR, and signal P3 to write to the MAR. 44 4.13 A Discussion on Decoding Here is the complete signal sequence for MARIEs

Add instruction: P3 P2 P1 P0 T0: P4 P3 T1: A0 P5 P1 P0 T2: Cr T3: MAR X MBR M[MAR] AC AC + MBR [Reset counter] These signals are ANDed with combinational logic to

bring about the desired machine behavior. The next slide shows the timing diagram for this instruction.. 45 4.13 Decoding Notice the concurrent signal states during each machine cycle: C0 through C3. P3 P2 P1 P0 T0: MAR X P4 P3 T1: MBR M[MAR]

A0 P5 P1 P0 T2: AC AC + MBR Cr T3: [Reset counter] 46 4.13 A Discussion on Decoding We note that the signal pattern just described is the same whether our machine used hardwired or microprogrammed control. In hardwired control, the bit pattern of machine instruction in the IR is decoded by combinational logic.

The decoder output works with the control signals of the current system state to produce a new set of control signals. A block diagram of a hardwired control unit is shown on the following slide. 47 4.13 A Discussion on Decoding 48 4.13 A Discussion on Decoding

MARIE's instruction decoder. (Partial.) 49 4.13 A Discussion on Decoding A ring counter

that counts from 0 to 5 50 This is the hardwired logic for MARIEs Add = 0011 instruction.

51

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