Chapter 2 - TMS320C6000 Architectural Overview

Chapter 2 - TMS320C6000 Architectural Overview

Chapter 2 TMS320C6000 Architectural Overview Learning Objectives hapter 2, Slide 2 Describe C6000 CPU architecture. Introduce some basic instructions. Describe the C6000 memory map. Provide an overview of the peripherals. Dr. Nai General DSP System Block Diagram Internal Memory Internal Buses External Memory hapter 2, Slide 3 Central Processing Unit P E R I P H E R A L S

Dr. Nai Implementation of Sum of Products (SOP) It has been shown in Chapter 1 that SOP is the key element for most DSP algorithms. So lets write the code for this algorithm and at the same time discover the C6000 architecture. hapter 2, Slide 4 N Y = n = 1 an * xn = a1 * x1 + a2 * x2 +... + aN * xN Two basic operations are required for this algorithm. (1) Multiplication (2) Addition Therefore two basic instructions are required Dr. Nai Implementation of Sum of Products (SOP) So lets implement the SOP algorithm! N Y = an * xn n = 1 = a1 * x1 + a2 * x2 +... + aN * xN

The implementation in this module will be done in assembly. hapter 2, Slide 5 Two basic operations are required for this algorithm. (1) Multiplication (2) Addition Therefore two basic instructions are required Dr. Nai hapter 2, Slide 6 Multiply (MPY) N Y = n = 1 an * xn = a1 * x1 + a2 * x2 +... + aN * xN The multiplication of a1 by x1 is done in assembly by the following instruction: MPY a1, x1, Y This instruction is performed by a multiplier unit that is called .M Dr. Nai Multiply (.M unit) 40 Y = an * xn

n = 1 .M .M The . M unit performs multiplications in hardware MPY .M a1, x1, Y Note: 16-bit by 16-bit multiplier provides a 32-bit result. hapter 2, Slide 7 32-bit by 32-bit multiplier provides a 64-bit result. Dr. Nai hapter 2, Slide 8 Addition (.?) 40 Y = an * xn n = 1 .M .M .?.? MPY .M a1, x1, prod ADD .? Y, prod, Y

Dr. Nai Add (.L unit) 40 Y = an * xn n = 1 .M .M .L .L MPY .M a1, x1, prod ADD .L Y, prod, Y RISC processors such as the C6000 use registers to hold the operands, so lets change this code. hapter 2, Slide 9 Dr. Nai Register File - A 40 Register File A A0 A1 A2 A3 Y = an * xn

a1 x1 n = 1 prod Y .M .M . . . .L .L MPY .M a1, x1, prod ADD .L Y, prod, Y A15 32-bits Let us correct this by replacing a, x, prod and Y by the registers as shown above. hapter 2, Slide 10 Dr. Nai Specifying Register Names 40

Register File A A0 A1 A2 A3 Y = an * xn a1 x1 n = 1 prod Y .M .M . . . .L .L MPY .M A0, A1, A3 ADD .L A4, A3, A4 A15 32-bits The registers A0, A1, A3 and A4 contain the values to

be used by the instructions. hapter 2, Slide 11 Dr. Nai Specifying Register Names 40 Register File A A0 A1 A2 A3 Y = an * xn a1 x1 n = 1 prod Y .M .M . . . .L .L MPY .M A0, A1, A3 ADD

.L A4, A3, A4 A15 32-bits Register File A contains 16 registers (A0 -A15) which are 32-bits wide. hapter 2, Slide 12 Dr. Nai Data loading Register File A A0 A1 A2 A3 Q: How do we load the operands into the registers? a1 x1 prod Y .M .M . . . .L .L A15 hapter 2, Slide 13

32-bits Dr. Nai Load Unit .D Register File A A0 A1 A2 A3 a1 x1 prod Y .M .M . . . .L .L A: The operands are loaded into the registers by loading them from the memory using the .D unit. .D .D A15 hapter 2, Slide 14 Q: How do we load the operands into the registers? 32-bits

Data Memory Dr. Nai Load Unit .D Register File A A0 A1 A2 A3 a1 x1 prod Y .M .M . . . .L .L .D .D A15 hapter 2, Slide 15 It is worth noting at this stage that the only way to access memory is through the .D unit. 32-bits Data Memory Dr. Nai Load Instruction Register File A

A0 A1 A2 A3 a1 x1 prod Y .M .M . . . .L .L .D .D A15 hapter 2, Slide 16 Q: Which instruction(s) can be used for loading operands from the memory to the registers? 32-bits Data Memory Dr. Nai Load Instructions (LDB, LDH,LDW,LDDW) Register File A A0 A1 A2 A3

a1 x1 prod Y .M .M . . . .L .L A: The load instructions. .D .D A15 hapter 2, Slide 17 Q: Which instruction(s) can be used for loading operands from the memory to the registers? 32-bits Data Memory Dr. Nai Using the Load Instructions Before using the load unit you have to be aware that this processor is byte addressable, which means that each byte is represented by a unique address. Data

00000000 00000002 00000004 00000006 00000008 Also the addresses are 32-bit wide. hapter 2, Slide 18 address FFFFFFFF 16-bits Dr. Nai Using the Load Instructions The syntax for the load instruction is: LD *Rn,Rm Where: Rn is a register that contains the address of the operand to be loaded Data address a1 x1 00000000 00000002 00000004 00000006 00000008 prod Y

and Rm is the destination register. hapter 2, Slide 19 FFFFFFFF 16-bits Dr. Nai Using the Load Instructions The syntax for the load instruction is: LD *Rn,Rm The question now is how many bytes are going to be loaded into the destination register? hapter 2, Slide 20 Data address a1 x1 00000000 00000002 00000004 00000006 00000008 prod Y FFFFFFFF 16-bits Dr. Nai Using the Load Instructions

The syntax for the load instruction is: LD *Rn,Rm The answer, is that it depends on the instruction you choose: Data address a1 x1 00000000 00000002 00000004 00000006 00000008 prod Y LDB: loads one byte (8-bit) LDH: loads half word (16-bit) LDW: loads a word (32-bit) LDDW: loads a double word (64bit) Note: LD on its own does not exist. hapter 2, Slide 21 FFFFFFFF 16-bits Dr. Nai Using the Load Instructions The syntax for the load instruction is: 1

Data 0 0xA 0xB 0xC 0xD 0x2 0x1 0x4 0x3 If we assume that A5 = 0x4 then: 0x6 0x5 (1) LDB *A5, A7 ; gives A7 = 0x00000001 0x8 0x7 LD *Rn,Rm Example: address 00000000 00000002 00000004 00000006 00000008 (2) LDH *A5,A7; gives A7 = 0x00000201

(3) LDW *A5,A7; gives A7 = 0x04030201 (4) LDDW *A5,A7:A6; gives A7:A6 = 0x0807060504030201 hapter 2, Slide 22 FFFFFFFF 16-bits Dr. Nai Using the Load Instructions The syntax for the load instruction is: LD *Rn,Rm Question: If data can only be accessed by the load instruction and the .D unit, how can we load the register pointer Rn in the first place? hapter 2, Slide 23 Data address 0xA 0xB 0xC 0xD 0x2 0x1 0x4 0x3

0x6 0x5 0x8 0x7 00000000 00000002 00000004 00000006 00000008 FFFFFFFF 16-bits Dr. Nai Loading the Pointer Rn The instruction MVKL will allow a move of a 16-bit constant into a register as shown below: MVKL .? a, A5 (a is a constant or label) How many bits represent a full address? 32 bits hapter 2, Slide 24 So why does the instruction not allow a 32-bit move? All instructions are 32-bit wide (see instruction opcode). Dr. Nai

Loading the Pointer Rn To solve this problem another instruction is available: MVKH eg. MVKH .? a, A5 (a is a constant or label) hapter 2, Slide 25 ah al a ah x A5 Finally, to move the 32-bit address to a register we can use: MVKL a, A5 MVKH a, A5 Dr. Nai

Loading the Pointer Rn Always use MVKL then MVKH, look at the following examples: Example 1 A5 = 0x87654321 MVKL 0x1234FABC, A5 A5 = 0xFFFFFABC (sign extension) MVKH 0x1234FABC, A5 A5 = 0x1234FABC ; OK Example 2 MVKH A5 = 0x12344321 hapter 2, Slide 26 0x1234FABC, A5 MVKL 0x1234FABC, A5 A5 = 0xFFFFFABC ; Wrong Dr. Nai LDH, MVKL and MVKH Register File A A0 A1 a

x A2 A3 A4 prod Y .M .M . . . .L .L .D .D A15 hapter 2, Slide 27 MVKL MVKH pt1, A5 pt1, A5 MVKL MVKH pt2, A6 pt2, A6 LDH .D *A5, A0

LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 32-bits pt1 and pt2 point to some locations Data Memory in the data memory. Dr. Nai Creating a loop So far we have only implemented the SOP for one tap only, i.e. Y= a1 * x1 So lets create a loop so that we can implement the SOP for N Taps. hapter 2, Slide 28 MVKL MVKH pt1, A5 pt1, A5

MVKL MVKH pt2, A6 pt2, A6 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 Dr. Nai Creating a loop So far we have only implemented the SOP for one tap only, i.e. Y= a1 * x1 With the C6000 processors there are no dedicated instructions such as block repeat. The loop is created

using the B instruction. So lets create a loop so that we can implement the SOP for N Taps. hapter 2, Slide 29 Dr. Nai What are the steps for creating a loop 1. Create a label to branch to. 2. Add a branch instruction, B. 3. Create a loop counter. 4. Add an instruction to decrement the loop counter. 5. Make the branch conditional based on the value in the loop counter. hapter 2, Slide 30 Dr. Nai hapter 2, Slide 31 1. Create a label to branch to loop MVKL MVKH pt1, A5 pt1, A5 MVKL MVKH pt2, A6 pt2, A6 LDH

.D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 Dr. Nai hapter 2, Slide 32 2. Add a branch instruction, B. loop MVKL MVKH pt1, A5 pt1, A5 MVKL MVKH pt2, A6 pt2, A6 LDH

.D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .? loop Dr. Nai Which unit is used by the B instruction? Register File A A0 A1 A2 A3 a x .S .S

prod Y .M .M .M .M . . . .L .L .L .L .D .D .D .D A15 hapter 2, Slide 33 loop MVKL MVKH pt1, A5 pt1, A5 MVKL MVKH pt2, A6 pt2, A6 LDH .D

*A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .? loop 32-bits Data Memory Dr. Nai Which unit is used by the B instruction? Register File A A0 A1 A2 A3 a x .S

.S prod Y .M .M .M .M . . . .L .L .L .L .D .D .D .D A15 hapter 2, Slide 34 loop MVKL .S MVKH .S pt1, A5 pt1, A5 MVKL .S MVKH .S pt2, A6 pt2, A6 LDH

.D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .S loop 32-bits Data Memory Dr. Nai 3. Create a loop counter. Register File A A0 A1 A2 A3 a x

.S .S prod Y .M .M .M .M . . . .L .L .L .L .D .D .D .D A15 hapter 2, Slide 35 32-bits loop MVKL .S MVKH .S pt1, A5 pt1, A5 MVKL .S MVKH .S MVKL .S pt2, A6

pt2, A6 count, B0 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .S loop B registers will be introduced later Data Memory Dr. Nai 4. Decrement the loop counter Register File A A0 A1 A2

A3 a x .S .S prod Y .M .M .M .M . . . .L .L .L .L .D .D .D .D A15 hapter 2, Slide 36 32-bits loop MVKL .S MVKH .S pt1, A5 pt1, A5

MVKL .S MVKH .S MVKL .S pt2, A6 pt2, A6 count, B0 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop

Data Memory Dr. Nai 5. Make the branch conditional based on the value in the loop counter What is the syntax for making instruction conditional? [condition] Instruction Label e.g. [B1] B loop (1) The condition can be one of the following registers: A1, A2, B0, B1, B2. (2) Any instruction can be conditional. hapter 2, Slide 37 Dr. Nai 5. Make the branch conditional based on the value in the loop counter The condition can be inverted by adding the exclamation symbol ! as follows: [!condition] Instruction Label e.g. [!B0]B B0]B loop ;branch if B0 = 0 [B0] B loop ;branch if B0 != 0 hapter 2, Slide 38 Dr. Nai 5. Make the branch conditional

MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 Register File A A0 A1 A2 A3 a x .S .S prod Y .M .M .M .M . . . .L .L .L .L .D .D .D .D A15 hapter 2, Slide 39 32-bits MVKL .S2 pt2, A6

MVKH .S2 pt2, A6 MVKL .S2 count, B0 loop [B0] LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop Data Memory

Dr. Nai More on the Branch Instruction (1) With this processor all the instructions are encoded in a 32-bit. Therefore the label must have a dynamic range of less than 32-bit as the instruction B has to be coded. 32-bit B Case 1: hapter 2, Slide 40 21-bit relative address B .S1 label Relative branch. Label limited to +/- 220 offset. Dr. Nai More on the Branch Instruction (2) By specifying a register as an operand instead of a label, it is possible to have an absolute branch. This will allow a dynamic range of 232. 32-bit B Case 2: hapter 2, Slide 41 B .S2 5-bit register code register

Absolute branch. Operates on .S2 ONLY! Dr. Nai Testing the code MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 This code performs the following operations: loop LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 However, we would like to perform: ADD .L A4, A3, A4

a0*x0 + a1*x1 + a2*x2 + + aN*xN SUB .S B0, 1, B0 B .S loop a0*x0 + a0*x0 + a0*x0 + + a0*x0 hapter 2, Slide 42 [B0] Dr. Nai Modifying the pointers MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 The solution is to modify the pointers hapter 2, Slide 43 loop A5 and A6. [B0] LDH .D *A5, A0

LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop Dr. Nai hapter 2, Slide 44 Indexing Pointers Syntax Description *R Pointer

Pointer Modified No In this case the pointers are used but not modified. R can be any register Dr. Nai Indexing Pointers Syntax Description *R *+R[disp] *-R[disp] Pointer + Pre-offset - Pre-offset Pointer Modified No No No In this case the pointers are modified BEFORE being used and RESTORED to their previous values. [disp] specifies the number of elements size in DW (64-bit), W (32-bit), H (16-bit), or B (8-bit). disp = R or 5-bit constant. R can be any register. hapter 2, Slide 45

Dr. Nai Indexing Pointers Syntax Description *R *+R[disp] *-R[disp] *++R[disp] *--R[disp] Pointer + Pre-offset - Pre-offset Pre-increment Pre-decrement Pointer Modified No No No Yes Yes In this case the pointers are modified BEFORE being used and NOT RESTORED to their Previous Values. hapter 2, Slide 46 Dr. Nai Indexing Pointers Syntax Description *R *+R[disp] *-R[disp] *++R[disp]

*--R[disp] *R++[disp] *R--[disp] Pointer + Pre-offset - Pre-offset Pre-increment Pre-decrement Post-increment Post-decrement Pointer Modified No No No Yes Yes Yes Yes In this case the pointers are modified AFTER being used and NOT RESTORED to their Previous Values. hapter 2, Slide 47 Dr. Nai Indexing Pointers Syntax Description *R *+R[disp] *-R[disp] *++R[disp] *--R[disp] *R++[disp] *R--[disp] Pointer

+ Pre-offset - Pre-offset Pre-increment Pre-decrement Post-increment Post-decrement hapter 2, Slide 48 Pointer Modified No No No Yes Yes Yes Yes [disp] specifies # elements - size in DW, W, H, or B. disp = R or 5-bit constant. R can be any register. Dr. Nai Modify and testing the code MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 This code now performs the following operations: loop a0*x0 + a1*x1 + a2*x2 + ... + aN*xN hapter 2, Slide 49

[B0] LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop Dr. Nai Store the final result MVKL .S2 pt1, A5 MVKH .S2 pt1, A5

MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 This code now performs the following operations: loop a0*x0 + a1*x1 + a2*x2 + ... + aN*xN hapter 2, Slide 50 [B0] LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0

B .S loop STH .D A4, *A7 Dr. Nai Store the final result MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 count, B0 The Pointer A7 has not been initialised. hapter 2, Slide 51 loop [B0] LDH .D *A5++, A0 LDH .D *A6++, A1 MPY

.M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop STH .D A4, *A7 Dr. Nai Store the final result MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 MVKL .S2 pt3, A7 MVKH .S2 pt3, A7 MVKL .S2 count, B0 The Pointer A7 is now initialised. hapter 2, Slide 52

loop [B0] LDH .D *A5++, A0 LDH .D *A6++, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop STH .D

A4, *A7 Dr. Nai hapter 2, Slide 53 What is the initial value of A4? MVKL .S2 pt1, A5 MVKH .S2 pt1, A5 MVKL .S2 pt2, A6 MVKH .S2 pt2, A6 A4 is used as an accumulator, so it needs to be reset to zero. loop [B0] MVKL MVKH MVKL ZERO LDH .S2 .S2 .S2 .L .D pt3, A7 pt3, A7 count, B0 A4 *A5++, A0 LDH .D *A6++, A1

MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop STH .D A4, *A7 Dr. Nai Increasing the processing power! Register File A A0 A1 A2 A3 A4 .S1 .S1 .M1 .M1

. . . .D1 .D1 A15 hapter 2, Slide 54 .L1 .L1 How can we add more processing power to this processor? 32-bits Data Memory Dr. Nai Increasing the processing power! Register File A A0 A1 A2 A3 A4 .S1 .S1 .M1 .M1 . . . (2) Increase the number

of Processing units. .D1 .D1 A15 hapter 2, Slide 55 .L1 .L1 (1) Increase the clock frequency. 32-bits Data Memory Dr. Nai To increase the Processing Power, this processor has two sides (A and B or 1 and 2) Register File A A0 A1 A2 A3 A4 . . . A15 hapter 2, Slide 56 Register File B .S1 .S1 .S2 .S2

.M1 .M1 .M2 .M2 .L1 .L1 .L2 .L2 .D1 .D1 .D2 .D2 32-bits B0 B1 B2 B3 B4 . . . B15 32-bits Data Memory Dr. Nai Can the two sides exchange operands in order to increase performance? Register File A A0 A1 A2 A3 A4

. . . A15 hapter 2, Slide 57 Register File B .S1 .S1 .S2 .S2 .M1 .M1 .M2 .M2 .L1 .L1 .L2 .L2 .D1 .D1 .D2 .D2 32-bits B0 B1 B2 B3 B4 . .

. B15 32-bits Data Memory Dr. Nai The answer is YES but there are limitations. To exchange operands between the two sides, some cross paths or links are required. What is a cross path? A cross path links one side of the CPU to the other. There are two types of cross paths: hapter 2, Slide 58 Data cross paths. Address cross paths. Dr. Nai Data Cross Paths Data cross paths can also be referred to as register file cross paths.

These cross paths allow operands from one side to be used by the other side. There are only two cross paths: hapter 2, Slide 59 one path which conveys data from side B to side A, 1X. one path which conveys data from side A to side B, 2X. Dr. Nai hapter 2, Slide 60 TMS320C67x Data-Path Dr. Nai Data Cross Paths Data cross paths only apply to the .L, .S and .M units. The data cross paths are very useful, however there are some limitations in their use. hapter 2, Slide 61 Dr. Nai

Data Cross Path Limitations .L1 .M1 .S1 A (1) The destination register must be on same side as unit. (2) Source registers - up to one cross path per execute packet per side. 2 x 1 x B Execute packet: group of instructions that execute simultaneously. hapter 2, Slide 62 Dr. Nai hapter 2, Slide 63 Data Cross Path Limitations eg: ADD MPY SUB || ADD

.L1 .M1 .S1 .L1x .M1x .S1x .L1x A A0,A1,B2 A0,B6,A9 A8,B2,A8 A0,B0,A2 || Means that the SUB and ADD belong to the same fetch packet, therefore execute simultaneously. 2 x 1 x B Dr. Nai hapter 2, Slide 64 Data Cross Path Limitations eg: ADD MPY SUB

|| ADD .L1 .M1 .S1 .L1x .M1x .S1x .L1x A A0,A1,B2 A0,B6,A9 A8,B2,A8 A0,B0,A2 2 x 1 x B NOT VALID! Dr. Nai hapter 2, Slide 65 Data Cross Paths for both sides .L1 .M1 .S1

.L2 .M2 .S2 A 2 x 1 x B Dr. Nai hapter 2, Slide 66 Address cross paths Data Addr A .D1 (1) The pointer must be on the same side of the unit. LDW.D1T1 LDW.D1T1 STW.D1T1 STW.D1T1 *A0,A5 *A0,A5 A5,*A0

A5,*A0 Dr. Nai Load or store to either side Data1 DA1 = T1 DA2 = T2 hapter 2, Slide 67 Data2 A5 .D1 LDW.D1T1 LDW.D1T1 LDW.D1T2 LDW.D1T2 *A0 *A0,A5 *A0,A5 *A0,B5 *A0,B5 B5 A B Dr. Nai Standard Parallel Loads Data1 DA1 = T1 DA2 = T2 hapter 2, Slide 68 A5

.D1 *A0 .D2 *B0 LDW.D1T1 LDW.D1T1 || || LDW.D2T2 LDW.D2T2 *A0,A5 *A0,A5 *B0,B5 *B0,B5 B5 A B Dr. Nai Parallel Load/Store using address cross paths Data1 DA1 = T1 DA2 = T2 hapter 2, Slide 69 A5 .D1 *A0 .D2 *B0

LDW.D1T2 LDW.D1T2 || || STW.D2T1 STW.D2T1 *A0,B5 *A0,B5 A5,*B0 A5,*B0 B5 A B Dr. Nai Fill the blanks ... Does this work? Data1 DA1 = T1 DA2 = T2 hapter 2, Slide 70 .D1 *A0 .D2 *B0 LDW.D1__ LDW.D1__ || || STW.D2__ STW.D2__ A B *A0,B5

*A0,B5 B6,*B0 B6,*B0 Dr. Nai Not Allowed! Parallel accesses: both cross or neither cross Data1 DA2 = T2 hapter 2, Slide 71 .D1 *A0 .D2 *B0 B5 LDW.D1 LDW.D1T2 T2 || || STW.D2 STW.D2T2 T2 A B *A0,B5 *A0,B5 B6 B6,*B0 B6,*B0 Dr. Nai Conditions Dont Use Cross Paths

hapter 2, Slide 72 If a conditional register comes from the opposite side, it does NOT use a data or address cross-path. Examples: [B2] [A1] ADD LDW .L1 .D2 A2,A0,A4 *B0,B5 Dr. Nai hapter 2, Slide 73 C62x Data-Path Summary CPU Ref Guide Full CPU Datapath (Pg 2-2) Dr. Nai hapter 2, Slide 74 C67x Data-Path Summary C67x Dr. Nai Cross Paths - Summary

Data Address hapter 2, Slide 75 Destination register on same side as unit. Source registers - up to one cross path per execute packet per side. Use x to indicate cross-path. Pointer must be on same side as unit. Data can be transferred to/from either side. Parallel accesses: both cross or neither cross. Conditionals Dont Use Cross Paths. Dr. Nai Code Review (using side A only) 40 Y = an * xn n = 1 MVK loop: LDH LDH MPY ADD SUB [A2] B

STH .S1 .D1 .D1 .M1 .L1 .L1 .S1 .D1 40, A2 *A5++, A0 *A6++, A1 A0, A1, A3 A3, A4, A4 A2, 1, A2 loop A4, *A7 ; A2 = 40, loop count ; A0 = a(n) ; A1 = x(n) ; A3 = a(n) * x(n) ; Y = Y + A3 ; decrement loop count ; if A2 0, branch ; *A7 = Y Note: Assume that A4 was previously cleared and the pointers are initialised. hapter 2, Slide 76 Dr. Nai Let us have a look at the final details concerning the functional units. Consider first the case of the .L and .S units. hapter 2, Slide 77 Dr. Nai

Operands - 32/40-bit Register, 5-bit Constant Operands can be: 5-bit constants (or 16-bit for MVKL and MVKH). 32-bit registers. 40-bit Registers. However, we have seen that registers are only 32-bit. So where do the 40-bit registers come from? hapter 2, Slide 78 Dr. Nai Operands - 32/40-bit Register, 5-bit Constant A 40-bit register can be obtained by concatenating two registers. However, there are 3 conditions that need to be respected: hapter 2, Slide 79 The registers must be from the same side. The first register must be even and the second

odd. The registers must be consecutive. Dr. Nai Operands - 32/40-bit Register, 5-bit Constant hapter 2, Slide 80 All combinations of 40-bit registers are shown below: 40-bit Reg : odd even 8 32 40-bit Reg : odd even 8 32 A1:A0 B1:B0

A3:A2 B3:B2 A5:A4 B5:B4 A7:A6 B7:B6 A9:A8 B9:B8 A11:A10 B11:B10 A13:A12 B13:B12 A15:A14 B15:B14 Dr. Nai Operands - 32/40-bit Register, 5-bit Constant hapter 2, Slide 81 instr instr .unit .unit , , , , 32-bit Reg 5-bit

Const 32-bit Reg 40-bit Reg < src > < src > .L or .S < dst > 32-bit Reg 40-bit Reg Dr. Nai Operands - 32/40-bit Register, 5-bit Constant instr instr .unit .unit , , , , 32-bit Reg hapter 2, Slide 82 5-bit Const 32-bit Reg 40-bit Reg

< src > < src > .L or .S < dst > 32-bit Reg 40-bit Reg Dr. Nai Operands - 32/40-bit Register, 5-bit Constant instr instr .unit .unit , , , , 32-bit Reg hapter 2, Slide 83 5-bit Const 32-bit Reg 40-bit Reg < src > < src > .L or .S OR.L1

A0, A1, A2 < dst > 32-bit Reg 40-bit Reg Dr. Nai Operands - 32/40-bit Register, 5-bit Constant instr instr .unit .unit , , , , 32-bit Reg hapter 2, Slide 84 5-bit Const 32-bit Reg < src > < src > .L or .S < dst > 32-bit Reg 40-bit Reg OR.L1 ADD.L2

A0, A1, A2 -5, B3, B4 40-bit Reg Dr. Nai Operands - 32/40-bit Register, 5-bit Constant instr instr .unit .unit , , , , 32-bit Reg hapter 2, Slide 85 5-bit Const 32-bit Reg < src > < src > .L or .S < dst > 32-bit Reg 40-bit Reg OR.L1 ADD.L2 ADD.L1 A0, A1, A2

-5, B3, B4 A2, A3, A5:A4 40-bit Reg Dr. Nai Operands - 32/40-bit Register, 5-bit Constant instr instr .unit .unit , , , , 32-bit Reg hapter 2, Slide 86 5-bit Const 32-bit Reg < src > < src > .L or .S < dst > 32-bit Reg 40-bit Reg 40-bit Reg OR.L1 ADD.L2 ADD.L1

SUB.L1 A0, -5, A2, A2, A1, A2 B3, B4 A3, A5:A4 A5:A4, A5:A4 Dr. Nai Operands - 32/40-bit Register, 5-bit Constant instr instr .unit .unit , , , , 32-bit Reg hapter 2, Slide 87 5-bit Const 32-bit Reg < src > < src > .L or .S < dst > 32-bit Reg 40-bit Reg

40-bit Reg OR.L1 ADD.L2 ADD.L1 SUB.L1 ADD.L2 A0, A1, A2 -5, B3, B4 A2, A3, A5:A4 A2, A5:A4, A5:A4 3, B9:B8, B9:B8 Dr. Nai Register to register data transfer hapter 2, Slide 88 To move the content of a register (A or B) to another register (B or A) use the move MV Instruction, e.g.: MV A0, B0 MV B6, B7 To move the content of a control register to another register (A or B) or vice-versa use the MVC instruction, e.g.: MVC IFR, A0

MVC A0, IRP Dr. Nai hapter 2, Slide 89 TMS320C6000 Instruction Set Dr. Nai hapter 2, Slide 90 'C62x Instruction Set (by category) Arithmetic Logical ABS ADD ADDA ADDK ADD2 MPY MPYH NEG SMPY SMPYH SADD SAT SSUB SUB SUBA SUBC SUB2 ZERO AND CMPEQ CMPGT CMPLT NOT OR

SHL SHR SSHL XOR Bit Mgmt CLR EXT LMBD NORM SET Data Mgmt LDB/H/W MV MVC MVK MVKL MVKH MVKLH STB/H/W Program Ctrl B IDLE NOP Note: Refer to the 'C6000 CPU Reference Guide for more details. Dr. Nai hapter 2, Slide 91 'C62x Instruction Set (by unit) .S Unit ADD ADDK ADD2 AND B CLR EXT MV MVC

MVK MVKL MVKH MVKLH NEG NOT OR SET SHL SHR SSHL SUB SUB2 XOR ZERO .M Unit MPY MPYH SMPY SMPYH Other NOP IDLE .L Unit ABS ADD AND CMPE Q CMPG T CMPLT LMBD MV NEG

NORM NOT OR SADD SAT SSUB SUB SUBC XOR ZERO ADD ADDA LDB/H/W MV NEG STB/H/W SUB SUBA ZERO .D Unit Note: Refer to the 'C6000 CPU Reference Guide for more details. Dr. Nai ' C6700: Superset of Fixed-Point (by unit) .S Unit .S .S .L .L .D .D .M .M hapter 2, Slide 92

ADD ADDK ADD2 AND B CLR EXT MV MVC MVK MVKL MVKH NEG NOT OR SET SHL SHR SSHL SUB SUB2 XOR ZERO ABSSP ABSDP CMPGTSP CMPEQSP CMPLTSP CMPGTDP CMPEQDP CMPLTDP RCPSP RCPDP RSQRSP RSQRDP SPDP .D Unit ADD NEG ADDAB (B/H/W) STB

(B/H/W) ADDAD SUB LDB (B/H/W) SUBAB (B/H/W) LDDW ZERO MV .L Unit ABS ADD AND CMPEQ CMPGT CMPLT LMBD MV NEG NORM NOT OR SADD SAT SSUB SUB SUBC XOR ZERO ADDSP ADDDP SUBSP SUBDP INTSP INTDP SPINT DPINT SPRTUNC DPTRUNC DPSP

C67x .M Unit MPY MPYH MPYLH MPYHL SMPY SMPYH MPYSP MPYDP MPYI MPYID No Unit Used NOP IDLE Note: Refer to the 'C6000 CPU Reference Guide for more details. Dr. Nai Superset of Fixed-Point Control Registers Instruction Dispatch Advanced Instruction Packing Instruction Decode Emulation hapter 2, Slide 93 Advanced Emulation Registers (A0 - A15) Registers (B0 - B15)

Registers (A16 - A31) Registers (B16 - B31) L1 + + + + Interrupt Control Instruction Fetch S1 + + + + M1 x x x x X D1 + + X D2 + M2 X +

X x x x x S2 + + L2 + + + + + + C62x: Dual 32-Bit Load/Store C64x: Dual 64-Bit Load/Store C67x: Dual 64-Bit Load/32-Bit Store Dr. Nai 'C64x: Superset of C62x .S .S .D .D Dual/Quad Arith SADD2 SADDUS2 SADD4 Data Pack/Un PACK2 PACKH2 PACKLH2 PACKHL2 Bitwise Logical UNPKHU4

ANDN UNPKLU4 Shifts & Merge SWAP2 SPACK2 SHR2 SPACKU4 SHRU2 SHLMB SHRMB Dual Arithmetic Mem Access ADD2 LDDW SUB2 LDNW LDNDW Bitwise Logical STDW AND STNW ANDN STNDW OR XOR Load Constant MVK (5-bit) Address Calc. ADDAD hapter 2, Slide 94 Compares CMPEQ2 CMPEQ4 CMPGT2 CMPGT4 .L .L Branches/PC BDEC BPOS BNOP ADDKPC

Dual/Quad Arith ABS2 ADD2 ADD4 MAX MIN SUB2 SUB4 SUBABS4 Bitwise Logical ANDN .M .M Average AVG2 AVG4 Shifts ROTL SSHVL SSHVR Data Pack/Un PACK2 PACKH2 PACKLH2 PACKHL2 PACKH4 PACKL4 UNPKHU4 UNPKLU4 SWAP2/4 Multiplies MPYHI Shift & Merge MPYLI SHLMB MPYHIR SHRMB MPYLIR MPY2

Load Constant SMPY2 MVK (5-bit) Bit Operations DOTP2 DOTPN2 BITC4 DOTPRSU2 BITR DOTPNRSU2 DEAL DOTPU4 SHFL DOTPSU4 Move GMPY4 MVD XPND2/4 Dr. Nai hapter 2, Slide 95 TMS320C6000 Memory Dr. Nai Memory size per device Devices C6201, C6204, hapter 2, Slide 96 EMIFA P D = = 64 kB 64 kB

C6202 P D = = 256 kB 128 kB C6203 P D C6211 C6711 C6701 C6205 Internal = = 52M Bytes (32-bits wide) EMIFB N/A 384 kB 512 kB 128M Bytes (32-bits wide) L1P L1D L2

= = = 4 kB 4 kB 64 kB C6713 L1P L1D L2 = = = 4 kB 4 kB 256 kB 128M Bytes (32-bits wide) N/A C6411 DM642 L1P L1D L2 = = = 16 kB 16 kB 256 kB 128M Bytes

(32-bits wide) N/A C6414 C6415 C6416 L1P L1D L2 = = = 16 kB 16 kB 1 MB 256M Bytes (64-bits wide) C6712 64M Bytes (16-bits wide) N/A 64M Bytes (16-bits wide) Dr. Nai hapter 2, Slide 97 Internal Memory Summary Devices Internal (L2)

External C6211 C6711 C6713 64 kB 512M (32-bit wide) C6712 256 kB 512M (16-bit wide) Devices Internal (L2) C6414 C6415 C6416 1 MB DM642 256 kB C6411 256 kB External A: 1GB (64-bit) B: 256kB (16-bit) 1GB (64-bit) 256MB (32-bit)

LINK: TMS320C6000 DSP Generation Dr. Nai hapter 2, Slide 98 TMS320C6000 Peripherals Dr. Nai 'C6x System Block Diagram Memory External Memory .D1 .D2 .M1 .M2 .L1 .L2 .S1 .S2 Control Regs Regs (B0-B15) Regs (A0-A15) hapter 2, Slide 99 Internal Buses P E R I P H E R A L S CPU Dr. Nai

C6x Internal Buses Internal Memory A D External Interface A D x32 Peripherals A D C67x x32 Program Addr x32 Program Data x256 Data Addr - T1 x32 Data Data - T1 x32/64 Data Addr - T2 x32

Data Data - T2 x32/64 DMA Addr - Read x32 DMA Data - Read x32 DMA Addr - Write x32 DMA Data - Write x32 PC A regs B regs DMA can perform 64-bit data loads. hapter 2, Slide 100 Dr. Nai 'C6x System Block Diagram Memory Internal Buses EMIF .M1 .M2 .L1 .L2 .S1 .S2

Control Regs Regs (B0-B15) hapter 2, Slide 101 Regs (A0-A15) Extl Memory .D1 .D2 P E R I P H E R A L S CPU Dr. Nai 'C6x System Block Diagram Program RAM Data Ram Addr Internal Buses D (32) EMIF - Async hapter 2, Slide 102

.M1 .M2 .L1 .L2 .S1 .S2 Control Regs Regs (B0-B15) - Sync Regs (A0-A15) Extl Memory .D1 .D2 P E R I P H E R A L S CPU Dr. Nai 'C6000 Peripherals Parallel Comm Internal Memory GPIO External Memory

Internal Buses Serial Timers Ethernet Video Ports VCP / TCP .D1 .D2 .M1 .M2 .L1 .L2 .S1 .S2 Register Set B DMA, EDMA (Boot) Register Set A hapter 2, Slide 103 EMIF CPU PLL Dr. Nai EMIF Async SDRAM EMIF Internal Buses .D1 .D2 .M1 .M2 .L1 .L2

.S1 .S2 External External Memory Memory Interface Interface (EMIF) (EMIF) Register Set B Register Set A SBSRAM Internal Memory Glueless Gluelessaccess accessto toasync/sync async/syncmemory memory CPU Works with PC100/133 SDRAM (cheap, fast, Works with PC100/133 SDRAM (cheap, fast,and andeasy!) easy!) Byte-wide Byte-widedata dataaccess access 16, 16,32, 32,or

or64-bit 64-bitbus buswidths widths hapter 2, Slide 104 Dr. Nai HPI / XBUS / PCI Parallel Comm External Memory EMIF Internal Memory Internal Buses Parallel Parallel Communication Communication Interfaces Interfaces .M1 .M2 HPI: HPI: Register Set B Register Set A .D1 .D2 Dedicated, Dedicated,slave-only, slave-only,async async16/32-bit 16/32-bitbus busallows

allows host-P host-Paccess accessto toC6000 C6000memory memory .L1 .L2 XBUS: XBUS: Similar Similarto toHPI HPIbut butprovides provides .S1 .S2 Master/slave and sync modes Master/slave and sync modes Glueless CPUxfer Gluelessi/f i/fto toFIFOs FIFOs(up (upto tosingle-cycle single-cycle xferrate) rate) PCI: PCI: Standard Standard32-bit, 32-bit,33MHz/66MHz 33MHz/66MHzPCI PCIinterface interface These Theseinterfaces interfacesprovide providemeans

meansto tobootstrap bootstrapthe theC6000 C6000 hapter 2, Slide 105 Dr. Nai GPIO Parallel Comm Internal Memory GPIO External Memory EMIF Internal Buses .M1 .M2 .L1 .L2 .S1 .S2 Register Set B Register Set A .D1 .D2 General General Purpose Purpose Input/Output Input/Output (GPIO) (GPIO) CPU C64x

C64xand andC6713 C6713provide provide8-16 8-16bits bitsofofgeneral generalpurpose purposebit bitI/O I/O Use Usetotoobserve observeor orcontrol controlthe thesignal signalofofaasingle-pin single-pin hapter 2, Slide 106 Dr. Nai McBSP and Utopia Multi-Channel Buffered Parallel Multi-Channel Buffered Serial Serial Port Port (McBSP) (McBSP) 22(or Internal synchronous Comm (or3) 3)full-duplex, full-duplex, synchronousserial-ports serial-ports Up Memory

Upto to100 100Mb/sec Mb/secperformance performance GPIO Supports Supportsmulti-channel multi-channeloperation operation(T1, (T1,E1, E1,MVIP, MVIP,) ) External Memory EMIF Internal Buses Serial Register Set B Register Set A .D1 .D2 Multi-Channel (McASP) .M2 Multi-Channel Audio Audio Serial Serial Port Port.M1 (McASP) McBSP McBSPfeatures featuresplus plusmore more

Up Upto to88stereo stereolines lines(16 (16channels) channels) IIC IICsupport support On OnDM642, DM642,C6713 C6713 Utopia Utopia (C64x) (C64x) .L1 .L2 .S1 .S2 CPU ATM ATMconnection connection 50 50MHz MHzwide widearea areanetwork networkconnectivity connectivity hapter 2, Slide 107 Dr. Nai DMA / EDMA Parallel Comm

Internal Memory GPIO External Memory EMIF Internal Buses Serial .D1 .D2 .M1 .M2 .L1 .L2 Direct Direct Memory Memory Access Access (DMA (DMA // EDMA) EDMA) Transfers Transfersany anyset setof ofmemory memorylocations locationsto toanother another .S1 .S2 44//16 16//64 64channels

channels(transfer (transferparameter parametersets) sets) Transfers CPU Transferscan canbe betriggered triggeredby byany anyinterrupt interrupt(sync) (sync) Operates Operatesindependent independentof ofCPU CPU On Onreset, reset,provides providesbootstrap bootstrapfrom frommemory memory hapter 2, Slide 108 Register Set B Register Set A DMA, EDMA (Boot) Dr. Nai Timer/Counter Parallel Comm Internal

Memory GPIO External Memory EMIF Internal Buses Serial Timer Timer // Counter Counter Two Two(or (orthree) three)32-bit 32-bittimer/counters timer/counters Can generate interrupts Can generate interrupts Both Bothinput inputand andoutput outputpins pins hapter 2, Slide 109 .D1 .D2 .M1 .M2 .L1 .L2 .S1 .S2 Register Set B

Timers Register Set A DMA, EDMA (Boot) CPU Dr. Nai Ethernet MAC Parallel Comm Internal Memory GPIO External Memory EMIF Internal Buses Serial Ethernet Video Ports Ethernet (DM642 only) Ethernet (DM642 only) VCP / TCP 10/100 10/100Ethernet EthernetMAC MAC

Pins are muxed with PLL Pins are muxed withPCI PCI TCP/IP TCP/IPstack stackavailable availablefrom fromTI TI hapter 2, Slide 110 .D1 .D2 .M1 .M2 .L1 .L2 .S1 .S2 Register Set B Timers Register Set A DMA, EDMA (Boot) CPU Dr. Nai Video Ports Parallel Comm Internal Memory GPIO

External Memory EMIF Internal Buses Serial Video Video Ports Ports (DM642 (DM642only) only) Video Ports VCP / TCP .S1 .S2 Register Set B hapter 2, Slide 111 Register Set A Each for DMA, EDMA Eachconfigurable configurable forCapture Captureor orDisplay Display.D1 .D2 Dual or Dual8/10-bit 8/10-bitBT656 BT656 orraw rawmodes modes

(Boot) .M1 .M2 16/20-bit raw modes and 20-bit definition 16/20-bit raw modes and 20-bitY/C Y/Cfor forhigh high definition Horz Chroma Timers HorzScaling Scalingand and ChromaResampling ResamplingSupport Supportfor for8-bit 8-bitmodes modes .L1 .L2 Supports interface Supportstransport transport interfacemode mode Ethernet CPU PLL Dr. Nai VCP / TCP -- 3G Wireless Parallel Comm

Internal Memory GPIO External Internal Buses EMIF Memory Turbo TurboCoprocessor Coprocessor (TCP) (TCP) (C6416 (C6416only) only) Register Set B hapter 2, Slide 112 Register Set A Supports channels at 384 kbps Supports35 35data data channels at 384 kbps McBSPs 3GPP 3GPP//IS2000 IS2000Turbo Turbocoder coder .D1and .D2frame length

Programmable Utopia parameters include mode, rate Programmable parameters include mode, rate and frame length DMA, EDMA Viterbi (VCP) Viterbi Coprocessor Coprocessor (VCP) (C6416 (C6416only) only) .M1 .M2 Supports (Boot)channels Supports>>500 500voice voice channelsat at88kbps kbps .L1 .L2 Programmable parameters Programmabledecoder decoder parametersinclude includeconstraint constraintlength, length, Timers code rate, and frame length code rate, and frame length .S1 .S2 Video Ports VCP / TCP CPU PLL

Dr. Nai Phase Locked Loop (PLL) Parallel Comm Internal Memory GPIO External Memory EMIF Serial hapter 2, Slide 113 CLKIN CLKIN .M1 .M2 Output Output .L1 .L2 Register Set B Timers (Boot) Clock multiplier Clock multiplier Reduces and cost Timers ReducesEMI EMIEthernet and

cost Rate Video Ports Rateis isPin Pinselectable selectable VCP / TCP Input Input .D1 .D2 Register Set A PLL PLL DMA, EDMA (Boot) DMA, EDMA Internal Buses CLKOUT1 CLKOUT1 .S1 .S2 CLKOUT2 CLKOUT2 (reduced rate CPU (reduced rateclkout) clkout) PLL Dr. Nai Clock Cycle What is a clock cycle? The time between successive instructions C6000 C6000

CLKOUT1 (C6000 clock cycle) CLKIN PLL CLKOUT2 (, , or 1/6 CLKOUT1) When we talk about cycles ... CLKIN (MHz) PLL Rate CPU Clock Frequency CPU Clock Cycle Time MIPs (max) 60 x12 720 MHz 1.39 ns 5760 30 x10 300 MHz 3.33 ns 2400

50 x4 200 MHz 5 ns 1600 25 x4 100 MHz 10 ns 800 hapter 2, Slide 114 Dr. Nai 'C6000 Peripherals Summary Parallel Comm Internal Memory GPIO External Memory Internal Buses Serial Timers Ethernet

Timers Video Ports VCP / TCP .D1 .D2 .M1 .M2 .L1 .L2 .S1 .S2 Register Set B DMA, EDMA (Boot) Register Set A hapter 2, Slide 115 EMIF CPU PLL Dr. Nai C6x Family Part Numbering hapter 2, Slide 116 Example = TMS320LC6201PKGA200 TMS320 L C6

2 01 PKG A 200 = TI DSP = Place holder for voltage levels = C6x family = Fixed-point core = Memory/peripheral configuration = Pkg designator (actual letters TBD) = -40 to 85C (blank for 0 to 70C) = Core CPU speed in Mhz Dr. Nai Module 1 Exam 1. Functional Units a. How many can perform an ADD? Name them. b. Which support memory loads/stores? .M 2. Memory Map hapter 2, Slide 117 .S .D .L a. How many external ranges exist on C6201? Dr. Nai hapter 2, Slide 118 3. Conditional Code a. Which registers can be used as condl registers? b. Which instructions can be conditional? 4. Performance

a. What is the 'C6711 instruction cycle time? b. How can the 'C6711 execute 1200 MIPs? Dr. Nai hapter 2, Slide 119 5. Coding Problems a. Move contents of A0-->A1 Dr. Nai hapter 2, Slide 120 5. Coding Problems a. Move contents of A0-->A1 b. Move contents of CSR-->A1 c. Clear register A5 Dr. Nai hapter 2, Slide 121 5. Coding Problems (contd) d. A2 = A02 + A1 e. If (B1 0) then B2 = B5 * B6 f. A2 = A0 * A1 + 10 g. Load an unsigned constant (19ABCh) into register A6. Dr. Nai hapter 2, Slide 122 5. Coding Problems (contd) h. Load A7 with contents of mem1 and postincrement the selected pointer. Dr. Nai Module 1 Exam (solution)

1. Functional Units a. How many can perform an ADD? Name them. six; .L1, .L2, .D1, .D2, .S1, .S2 b. Which support memory loads/stores? .M 2. Memory Map hapter 2, Slide 123 .S .D .L a. How many external ranges exist on C6201? Four Dr. Nai hapter 2, Slide 124 3. Conditional Code a. Which registers can be used as condl registers? A1, A2, B0, B1, B2 b. Which instructions can be conditional? All of them 4. Performance a. What is the 'C6711 instruction cycle time? CLKOUT1 b. How can the 'C6711 execute 1200 MIPs? 1200 MIPs = 8 instructions (units) x 150 MHz Dr. Nai hapter 2, Slide 125 5. Coding Problems a. Move contents of A0-->A1 or or

MV ADD MPY .L1 .S1 .M1 A0, A1 A0, 0, A1 A0, 1, A1 (whats the problem with this?) Dr. Nai hapter 2, Slide 126 5. Coding Problems a. Move contents of A0-->A1 or or MV ADD MPY .L1 .S1 .M1 A0, A1 A0, 0, A1 A0, 1, A1 (A0 can only be a 16-bit value) b. Move contents of CSR-->A1 MVC CSR, A1 c. Clear register A5 or or or

or or ZERO .S1 SUB .L1 MPY .M1 CLR .S1 MVK .S1 XOR .L1 A5 A5, A5, A5 A5, 0, A5 A5, 0, 31, A5 0, A5 A5,A5,A5 Dr. Nai 5. Coding Problems (contd) d. A2 = A02 + A1 MPY.M1 ADD.L1 A0, A0, A2 A2, A1, A2 e. If (B1 0) then B2 = B5 * B6 [B1] MPY.M2 B5, B6, B2 f. A2 = A0 * A1 + 10 MPY A0, A1, A2 ADD 10, A2, A2 g. Load an unsigned constant (19ABCh) into register A6. value .equ 0x00019abc mvkl .s1 0x00019abc,a6 mvkl.s1 value,a6 mvkh .s1 0x00019abc,a6 mvkh.s1 value,a6

hapter 2, Slide 127 Dr. Nai 5. Coding Problems (contd) h. Load A7 with contents of mem1 and postincrement the selected pointer. x16 mem A7 mem1 load_mem1: hapter 2, Slide 128 10h MVKL .S1 mem1, A6 MVKH .S1 mem1, A6 LDH .D1 *A6++, A7 Dr. Nai Architecture

hapter 2, Slide 129 Links: C6711 data sheet: tms320c6711.pdf C6713 data sheet: tms320c6713.pdf C6416 data sheet: tms320c6416.pdf User guide: spru189f.pdf Errata: sprz173c.pdf Dr. Nai Chapter 2 TMS320C6000 Architectural Overview - End -

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