carrv.github.io

carrv.github.io

Federation: Open Source SoC Design Methodology Henry Cook, Principal Engineer June 22, 2019 How did turn into a $1B acquisition with only 13 employees?* * https://www.sigarch.org/open-source-hardware-stone-soups-and-not-stone-statues-please 4 Some research group Fabricate How did turn into a $1B acquisition with only 13 employees?* Coherent Chip MultiProcessor

15 * https://www.sigarch.org/open-source-hardware-stone-soups-and-not-stone-statues-please grad students 5 Why do silicon projects need experts from at least 14+ disciplines just to get started? 6 Tech Stack Tech Stack Readily-Available

Reusable Technology from techstacks.io Federation Tools Infrastructure Cloud Services 7 We Should Copy Innovations from the Software Industry open-source standards abstraction and code reuse composability and APIs productivity tooling commodity infrastructure 8

npm Enables Modular Web Development with Reusable Packages 9 Source: https://go.tiny.cloud/blog/a-guide-to-npm-the-node-js-package-manager/ npm Enables Javascript as Most Popular Programming Language

10 830.000 of packages 10 million users 30 billion packages downloads per month 90% of Web built of NPM packages NPM used everywhere: client, server, mobile, IoT Open source libraries availability is the major driving force for Language adoption [Leo2013] proven by NPM 70+ programming languages can be transpiled into JS, WebAssembly and published on NPM Federation: the action of forming states or organizations

into a single group with centralized control, within which smaller divisions have some degree of internal autonomy 11 Federation: a suite of open-source tools that SiFive is using to orchestrate modular SoC design workflows 12 Federation Tools Enable a Modular SoC Design Methodology IP Package 1 IP Package 2 IP Package 3

description description description dependencies dependencies dependencies Federation Tools 1. wit 2. DHH 3. wake Tool Package 1 commands

Workspace dependencies Tool Package 2 commands dependencies 1. 2. 3. 4. 13 Checkout workspace by analyzing dependencies of all packages Read descriptions of all IP packages, and generate assets that are needed for your chip design framework Collect commands from all tool packages, and generate a flow that is needed to build your SoC Design your SoC!

Tool Package 3 commands dependencies Federation Tools: wit, the Workspace Integration Tool https://github.com/sifive/wit wit is a tool for managing dependencies between git repos (Think of it like git submodules++) Supplement to (not a replacement for) git-based workflows Provides a flexible, yet reproducible and deterministic,

dependency-resolution algorithm generates a flattened directory structure in which each package may exist only once Enables multiple developers to simulatenously develop and deploy features that touch multiple repositories 14 Benefits of Small, Modular, and Reusable Packages IP Package IP Package IP Package Workspace 1.

2. 3. 4. 15 IP Package Tool Package Tool Package Workspace Tool Package Tool

Package Workspace Enforces an interface between components; makes it easier to reuse parts in different contexts and designs Encourages engineers to write unit tests for packages; makes it easier to filter bugs early Localizes regression test failures; makes it easier to root-cause them Enables fine-grained access control; makes it easier to open-source or give differential access to components Federation Tools: DH, or Design Hardware https://github.com/sifive/duh pronounced [dx] A manifest document format capturing integration intent Components, Designs, Configurations Ports, Bus Interfaces, Parameter Constraints, Registers,... Open-Source, JSON5, Extensible, and Generator-Agnostic Packaging tools for reusable hardware components and designs

16 Import: Verilog, SystemRDL, IP-XACT,... Authoring: Document creation, validation Export: Scala, Chisel, Verilog, IP-XACT, TLM, Documentation GUI: Query, Search, Configuration, Integration, Analysis Benefits of a Data Format that Describes IP Generators IP Package Rocket-Chip/CRAFT Framework (Chisel, FIRRTL, Diplomacy, TileLink) Your Own Chip Design Framework

Chisel BlackBox Wrappers TileLink Adapters Diplomacy Nodes DTS Entries Documentation Snippets Asset #1 Asset #2 Asset #3 Decouples the details of the chip design framework from the underlying IP generator; as a result: 1. Acts as a single source of truth, enforcing the DRY principle 2. Automatically generates assets that are needed for your chip design framework 3. Lowers the barrier to adopt your chip design framework 4. Makes it easier to use the IP package in other chip design frameworks 17 Federation Tools:

wake, orchestrating your build flow https://github.com/sifive/wake Wake is a tool and a language to make build systems composable Defines APIs to distinguish tooling choices from design flow steps Plugs packages build steps together with zero source changes 18 Federation Tools:

19 wake, orchestrating your build flow Dependent job execution: Which jobs to run next can depend on the results of previous jobs. All jobs may be dependent. Dependency analysis: Fails builds that will not be reproducible due to underspecified inputs dependencies. Prunes unused input dependencies so the job will not be re-run unless it must. You almost never need to tell wake what files a job builds; it knows. Build introspection: Wake keeps a database to record what it did. Query that database at any time to find out exactly how a file in your workspace got there. Intrinsically-parallel language While your build orchestration files describe a sequence of compilation steps, the wake language automatically extracts parallelism. Only true data dependencies cause wake to sequence jobs. Shared build caching If wake can prove it's safe, it will just copy the prebuilt files and save you time. PRs whose regression tests pass immediately, increasing productivity.

Case Study 1: Programmed-IO IP Package AXI MMIO IRQ block-pio-sifive PIO IP Block oenable 20 odata idata IP containing IO-programmable register map

DHH generation of wrapper containing Scala classes, Chisel blackbox, Diplomacy Nodes, Rocket-Chip traits Case Study 1: Programmed-IO IP Package Integration soc-testsocket-sifive RISC-V Test Socket rocket-chip Rocket Processor AXI MMIO IRQ PIO IP Block oenable odata

idata Loopback VIP Block idata = oenable ^ odata 21 https://github.com/sifive/block-pio-sifive block-pio-sifive block-pio-sifive Package Dependency Graph 22 Case Study 2: Cache Coherent SoC Template block-inclusivecache-sifive TL-C

InclusiveCache TL-UH 23 - Coherent, last-level inclusive cache Full directory bits stored with metadata tag TileLink adapter; drop-in replacement for tilelink.BroadcastHub SW-controlled flush interface Easily Config-ure size, ways, banking and sub-banking factors, external bandwidth, buffering Case Study 2: Cache Coherent System Template Integration soc-freedom-sifive Freedom SoC

FPGA Template Rocket Tile Rocket Tile Rocket Tile Rocket Tile rocket-chip TL SystemBus TL-C block-inclusivecache-sifive InclusiveCache TL-UH TL MemoryBus FPGA DDR Controller(s)

24 https://github.com/sifive/block-inclusivecache-sifive fpga-shells soc-freedom-sifive Package Dependency Graph 25 Open Source Package Progress (SiFive packages) Example projects

CRAFT framework APIs 26 https://github.com/sifive/api-generator-sifive https://github.com/sifive/api-scala-sifive https://github.com/sifive/api-chisel3-sifive https://github.com/sifive/api-firrtl-sifive https://github.com/sifive/environment-example-sifive Packaged blocks

https://github.com/sifive/block-pio-sifive https://github.com/sifive/soc-testsocket-sifive https://github.com/sifive/soc-iofpga-sifive https://github.com/sifive/soc-freedom-sifive https://github.com/sifive/block-inclusivecache-sifive https://github.com/sifive/block-pio-sifive https://github.com/sifive/block-nvdla-sifive Federation tools https://github.com/sifive/wit

https://github.com/sifive/duh https://github.com/sifive/wake Open Source Roadmap (Other Related Projects) 27 Rest of SiFives Freedom repository will be refactored into packages in Q3 of 2019 https://github.com/sifive/freedom => https://github.com/sifive/soc-freedom-sifive Rocket-Chip repository has been moved to the CHIPS Alliance github org will be refactored into packages in 2H of 2019 https://github.com/freechipsproject/rocket-chip => https://github.com/chipsalliance/rocket-chip

CHIPS Alliance: a subsidiary of the Linux Foundation Rocket-Chip Chisel / FIRRTL TileLink + OmniXtend Verilator SweRVE FuseSoC CocoTB https://github.com/chipsalliance/ https://chipsalliance.org/ SiFive Core Designer RISC-V Core IP Customization and Push-Button Configuration https://www.sifive.com/core-designer

Thanks! SiFive Chip Designer Coming soon Design Infrastructure EDA IP Fab Package/Test

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