Chapter 8 I/O I/O: Connecting to the Outside World Types of I/O devices characterized by: behavior: input, output, storage input: keyboard, motion detector, network interface output: monitor, printer, network interface storage: disk, CD-ROM data rate: how fast can data be transferred? keyboard: 100 bytes/sec disk: 30 MB/s network: 1 Mb/s - 1 Gb/s 8-2 I/O Controller Control/Status Registers CPU tells device what to do -- write to control register CPU checks whether task is done -- read status register
Data Registers CPU transfers data to/from device Control/Status CPU Output Data Graphics Controller Electronics display Device electronics performs actual operation pixels to screen, bits to/from disk, characters from keyboard 8-3 Programming Interface How are device registers identified / How do we get information to and from the I/O device
Memory-mapped vs. special instructions How is timing of transfer managed Asynchronous vs. synchronous Who controls transfer CPU (polling) vs. device (interrupts) 8-4 Memory-Mapped vs. I/O Instructions Instructions designate opcode(s) for I/O register and operation encoded in instruction Memory-mapped assign a memory address to each device register use data movement instructions (LD/ST) for control and data transfer
8-5 Transfer Timing I/O events generally happen much slower than CPU cycles. Timing of I/O is generally unpredictable Synchronous data supplied at a fixed, predictable rate CPU reads/writes every X cycles Asynchronous data rate less predictable CPU must synchronize with device, so that it doesnt miss data or write too quickly 8-6 Transfer Control Who determines when the next data transfer occurs? Polling CPU keeps checking status register until
new data arrives OR device ready for next data Simple to implement but can be inefficient Are we there yet? Are we there yet? Are we there yet? Interrupts Device sends a special signal to CPU when new data arrives OR device ready for next data CPU can be performing other tasks instead of polling device. Adds complexity, only useful if there is more than one task to do Not usually an issue in modern computer Wake me when we get there. 8-7 LC-3 Memory-mapped I/O (Table A.3) Location I/O Register
Function xFE00 Keyboard Status Reg (KBSR) Bit  is one when keyboard has received a new character. xFE02 Keyboard Data Reg (KBDR) Bits [7:0] contain the last character typed on keyboard. xFE04 Display Status Register (DSR)
Bit  is one when device ready to display another char on screen. xFE06 Display Data Register (DDR) Character written to bits [7:0] will be displayed on screen. Asynchronous devices synchronized through status registers Polling and Interrupts the details of interrupts will be discussed in Chapter 10 8-8 Input from Keyboard When a character is typed: its ASCII code is placed in bits [7:0] of KBDR (bits [15:8] are always zero)
the ready bit (KBSR) is set to one keyboard is disabled -- any typed characters will be ignored 15 8 7 keyboard data 0 KBDR 1514 ready bit 0 KBSR When KBDR is read: KBSR is set to zero
keyboard is enabled 8-9 Basic Input Routine POLL NO Polling new char? YES read character LDI R0, KBSRPtr BRzp POLL LDI R0, KBDRPtr ...
KBSRPtr .FILL xFE00 KBDRPtr .FILL xFE02 8-10 Simple Implementation: Memory-Mapped Input Address Control Logic determines whether MDR is loaded from Memory or from KBSR/KBDR. 8-11 Output to Monitor When Monitor is ready to display another character: the ready bit (DSR) is set to one 15 8 7
output data 0 DDR 1514 ready bit 0 DSR When data is written to Display Data Register: DSR is set to zero character in DDR[7:0] is displayed any other character data written to DDR is ignored (while DSR is zero) 8-12
Basic Output Routine POLL NO Polling screen ready? YES write character LDI R1, DSRPtr BRzp POLL STI R0, DDRPtr ... DSRPtr .FILL xFE04
DDRPtr .FILL xFE06 8-13 Simple Implementation: Memory-Mapped Output Sets LD.DDR or selects DSR as input. 8-14 Keyboard Echo Routine Usually, input character is also printed to screen. User gets feedback on character typed and knows its ok to type the next character. POLL1 POLL2 LDI BRzp
LDI LDI BRzp STI R0, KBSRPtr POLL1 R0, KBDRPtr R1, DSRPtr POLL2 R0, DDRPtr NO YES read character ... KBSRPtr
KBDRPtr DSRPtr DDRPtr .FILL .FILL .FILL .FILL xFE00 xFE02 xFE04 xFE06 new char? NO screen ready?
YES write character 8-15 Interrupt-Driven I/O External device can: (1) Force currently executing program to stop; (2) Have the processor satisfy the devices needs; and (3) Resume the stopped program as if nothing happened. Why? Polling consumes a lot of cycles, especially for rare events these cycles can be used for more computation. Example: Process previous input while collecting
current input. (See Example 8.1 in text.) 8-16 Interrupt-Driven I/O To implement an interrupt mechanism, we need: A way for the I/O device to signal the CPU that an interesting event has occurred. A way for the CPU to test whether the interrupt signal is set and whether its priority is higher than the current program. Generating Signal Software sets "interrupt enable" bit in device register. When ready bit is set and IE bit is set, interrupt is signaled. interrupt enable bit ready bit 1514 13 0
KBSR interrupt signal to processor 8-17 Priority Every instruction executes at a stated level of urgency. LC-3: 8 priority levels (PL0-PL7) Example: Payroll program runs at PL0. Nuclear power correction program runs at PL6. Its OK for PL6 device to interrupt PL0 program, but not the other way around. Priority encoder selects highest-priority device, compares to current processor priority level, and generates interrupt signal if appropriate. 8-18
Testing for Interrupt Signal CPU looks at signal between STORE and FETCH phases. If not set, continues with next instruction. If set, transfers control to interrupt service routine. FF NO Transfer Transfer to to ISR ISR YES interrupt signal? D D EA
EA OP OP EX EX More details in Chapter 10. S S 8-19 Full Implementation of LC-3 Memory-Mapped I/O Details skipped Because of interrupt enable bits, status registers (KBSR/DSR) must be written, as well as read. 8-20 Review Questions
What is the danger of not testing the DSR before writing data to the screen? Character not displayed or garbled What is the danger of not testing the KBSR before reading data from the keyboard? Read garbage or read same character multiple times What if the Monitor were a synchronous device, e.g., we know that it will be ready 1 microsecond after character is written. Can we avoid polling? How? Clocks/Timers What are advantages and disadvantages? Less overhead, clock skew 8-21 Review Questions Do you think polling is a good approach for other devices, such as a disk or a network interface? Probably not, inefficient, complex, blocking What is the advantage of using LDI/STI for accessing device registers? One vs two instructions
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